gpu: host1x: Set DMA mask
The default DMA mask covers a 32 bits address range, but host1x devices can address a larger range on TK1 and TX1. Set the DMA mask to the range addressable when we use the IOMMU to prevent the use of bounce buffers. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -23,6 +23,7 @@
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#define CREATE_TRACE_POINTS
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#include <trace/events/host1x.h>
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@ -68,6 +69,7 @@ static const struct host1x_info host1x01_info = {
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.nb_bases = 8,
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.init = host1x01_init,
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.sync_offset = 0x3000,
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.dma_mask = DMA_BIT_MASK(32),
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};
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static const struct host1x_info host1x02_info = {
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@ -77,6 +79,7 @@ static const struct host1x_info host1x02_info = {
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.nb_bases = 12,
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.init = host1x02_init,
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.sync_offset = 0x3000,
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.dma_mask = DMA_BIT_MASK(32),
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};
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static const struct host1x_info host1x04_info = {
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@ -86,6 +89,7 @@ static const struct host1x_info host1x04_info = {
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.nb_bases = 64,
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.init = host1x04_init,
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.sync_offset = 0x2100,
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.dma_mask = DMA_BIT_MASK(34),
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};
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static const struct host1x_info host1x05_info = {
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@ -95,6 +99,7 @@ static const struct host1x_info host1x05_info = {
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.nb_bases = 64,
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.init = host1x05_init,
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.sync_offset = 0x2100,
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.dma_mask = DMA_BIT_MASK(34),
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};
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static struct of_device_id host1x_of_match[] = {
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@ -148,6 +153,8 @@ static int host1x_probe(struct platform_device *pdev)
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if (IS_ERR(host->regs))
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return PTR_ERR(host->regs);
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dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
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if (host->info->init) {
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err = host->info->init(host);
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if (err)
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@ -96,6 +96,7 @@ struct host1x_info {
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int nb_mlocks; /* host1x: number of mlocks */
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int (*init)(struct host1x *); /* initialize per SoC ops */
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int sync_offset;
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u64 dma_mask; /* mask of addressable memory */
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};
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struct host1x {
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