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gpu: host1x: Set DMA mask

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The default DMA mask covers a 32 bits address range, but host1x devices
can address a larger range on TK1 and TX1. Set the DMA mask to the range
addressable when we use the IOMMU to prevent the use of bounce buffers.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Alexandre Courbot 2016-02-26 18:06:52 +09:00 committed by Thierry Reding
parent 92e963f50f
commit 097452e613
2 changed files with 8 additions and 0 deletions
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7
drivers/gpu/host1x/dev.c
View File

@ -23,6 +23,7 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/dma-mapping.h>
#define CREATE_TRACE_POINTS #define CREATE_TRACE_POINTS
#include <trace/events/host1x.h> #include <trace/events/host1x.h>
@ -68,6 +69,7 @@ static const struct host1x_info host1x01_info = {
.nb_bases = 8, .nb_bases = 8,
.init = host1x01_init, .init = host1x01_init,
.sync_offset = 0x3000, .sync_offset = 0x3000,
.dma_mask = DMA_BIT_MASK(32),
}; };
static const struct host1x_info host1x02_info = { static const struct host1x_info host1x02_info = {
@ -77,6 +79,7 @@ static const struct host1x_info host1x02_info = {
.nb_bases = 12, .nb_bases = 12,
.init = host1x02_init, .init = host1x02_init,
.sync_offset = 0x3000, .sync_offset = 0x3000,
.dma_mask = DMA_BIT_MASK(32),
}; };
static const struct host1x_info host1x04_info = { static const struct host1x_info host1x04_info = {
@ -86,6 +89,7 @@ static const struct host1x_info host1x04_info = {
.nb_bases = 64, .nb_bases = 64,
.init = host1x04_init, .init = host1x04_init,
.sync_offset = 0x2100, .sync_offset = 0x2100,
.dma_mask = DMA_BIT_MASK(34),
}; };
static const struct host1x_info host1x05_info = { static const struct host1x_info host1x05_info = {
@ -95,6 +99,7 @@ static const struct host1x_info host1x05_info = {
.nb_bases = 64, .nb_bases = 64,
.init = host1x05_init, .init = host1x05_init,
.sync_offset = 0x2100, .sync_offset = 0x2100,
.dma_mask = DMA_BIT_MASK(34),
}; };
static struct of_device_id host1x_of_match[] = { static struct of_device_id host1x_of_match[] = {
@ -148,6 +153,8 @@ static int host1x_probe(struct platform_device *pdev)
if (IS_ERR(host->regs)) if (IS_ERR(host->regs))
return PTR_ERR(host->regs); return PTR_ERR(host->regs);
dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
if (host->info->init) { if (host->info->init) {
err = host->info->init(host); err = host->info->init(host);
if (err) if (err)

1
drivers/gpu/host1x/dev.h
View File

@ -96,6 +96,7 @@ struct host1x_info {
int nb_mlocks; /* host1x: number of mlocks */ int nb_mlocks; /* host1x: number of mlocks */
int (*init)(struct host1x *); /* initialize per SoC ops */ int (*init)(struct host1x *); /* initialize per SoC ops */
int sync_offset; int sync_offset;
u64 dma_mask; /* mask of addressable memory */
}; };
struct host1x { struct host1x {