gpio: ws16c48: Migrate to the regmap API
The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver.
The WinSystems WS16C48 provides the following registers:
Offset 0x0-0x5: Port 0-5 I/O
Offset 0x6: Int_Pending
Offset 0x7: Page/Lock
Offset 0x8-0xA (Page 1): Pol_0-Pol_2
Offset 0x8-0xA (Page 2): Enab_0-Enab_2
Offset 0x8-0xA (Page 3): Int_ID0-Int_ID2
Port 0-5 I/O provides access to 48 lines of digital I/O across six
registers, each bit position corresponding to the respective line.
Writing a 1 to a respective bit position causes that output pin to sink
current, while writing a 0 to the same bit position causes that output
pin to go to a high-impedance state and allows it to be used an input.
Reads on a port report the inverted state (0 = high, 1 = low) of an I/O
pin when used in input mode. Interrupts are supported on Port 0-2.
Int_Pending is a read-only register that reports the combined state of
the INT_ID0 through INT_ID2 registers; an interrupt pending is indicated
when any of the low three bits are set.
The Page/Lock register provides the following bits:
Bit 0-5: Port 0-5 I/O Lock
Bit 6-7: Page 0-3 Selection
For Bits 0-5, writing a 1 to a respective bit position locks the output
state of the corresponding I/O port. Writing the page number to Bits 6-7
selects that respective register page for use.
Pol_0-Pol_2 are accessible when Page 1 is selected. Writing a 1 to a
respective bit position selects the rising edge detection interrupts for
that input line, while writing a 0 to the same bit position selects the
falling edge detection interrupts.
Enab_0-Enab_2 are accessible when Page 2 is selected. Writing a 1 to a
respective bit position enables interrupts for that input line, while
writing a 0 to that same bit position clears and disables interrupts for
that input line.
Int_ID0-Int_ID2 are accessible when Page 3 is selected. A respective bit
when read as a 1 indicates that an edge of the polarity set in the
corresponding polarity register was detected for the corresponding input
line. Writing any value to this register clears all pending interrupts
for the register.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/f59de81e80f7198bcfa9a15615c459c38b5d0e08.1680708357.git.william.gray@linaro.org/
Signed-off-by: William Breathitt Gray <william.gray@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
William Breathitt Gray
Bartosz Golaszewski
parent
1a200a3966
commit
0988ffa096
@ -998,7 +998,10 @@ config GPIO_WINBOND
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config GPIO_WS16C48
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tristate "WinSystems WS16C48 GPIO support"
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select ISA_BUS_API
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select REGMAP_IRQ
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select REGMAP_MMIO
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select GPIOLIB_IRQCHIP
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select GPIO_REGMAP
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help
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Enables GPIO support for the WinSystems WS16C48. The base port
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addresses for the devices may be configured via the base module
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@ -3,19 +3,18 @@
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* GPIO driver for the WinSystems WS16C48
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* Copyright (C) 2016 William Breathitt Gray
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*/
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#include <linux/bitmap.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/err.h>
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#include <linux/gpio/regmap.h>
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#include <linux/irq.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define WS16C48_EXTENT 10
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@ -31,371 +30,178 @@ static unsigned int num_irq;
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module_param_hw_array(irq, uint, irq, &num_irq, 0);
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MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
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/**
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* struct ws16c48_reg - device register structure
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* @port: Port 0 through 5 I/O
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* @int_pending: Interrupt Pending
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* @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0)
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* @pol_enab_int_id: Interrupt polarity, enable, and ID
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*/
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struct ws16c48_reg {
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u8 port[6];
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u8 int_pending;
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u8 page_lock;
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u8 pol_enab_int_id[3];
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#define WS16C48_DAT_BASE 0x0
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#define WS16C48_PAGE_LOCK 0x7
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#define WS16C48_PAGE_BASE 0x8
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#define WS16C48_POL WS16C48_PAGE_BASE
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#define WS16C48_ENAB WS16C48_PAGE_BASE
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#define WS16C48_INT_ID WS16C48_PAGE_BASE
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#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6)
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#define POL_PAGE u8_encode_bits(1, PAGE_LOCK_PAGE_FIELD)
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#define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD)
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#define INT_ID_PAGE u8_encode_bits(3, PAGE_LOCK_PAGE_FIELD)
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static const struct regmap_range ws16c48_wr_ranges[] = {
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regmap_reg_range(0x0, 0x5), regmap_reg_range(0x7, 0xA),
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};
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static const struct regmap_range ws16c48_rd_ranges[] = {
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regmap_reg_range(0x0, 0xA),
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};
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static const struct regmap_range ws16c48_volatile_ranges[] = {
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regmap_reg_range(0x0, 0x6), regmap_reg_range(0x8, 0xA),
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};
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static const struct regmap_access_table ws16c48_wr_table = {
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.yes_ranges = ws16c48_wr_ranges,
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.n_yes_ranges = ARRAY_SIZE(ws16c48_wr_ranges),
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};
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static const struct regmap_access_table ws16c48_rd_table = {
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.yes_ranges = ws16c48_rd_ranges,
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.n_yes_ranges = ARRAY_SIZE(ws16c48_rd_ranges),
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};
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static const struct regmap_access_table ws16c48_volatile_table = {
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.yes_ranges = ws16c48_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(ws16c48_volatile_ranges),
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};
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static const struct regmap_config ws16c48_regmap_config = {
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.reg_bits = 8,
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.reg_stride = 1,
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.val_bits = 8,
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.io_port = true,
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.wr_table = &ws16c48_wr_table,
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.rd_table = &ws16c48_rd_table,
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.volatile_table = &ws16c48_volatile_table,
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.cache_type = REGCACHE_FLAT,
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.use_raw_spinlock = true,
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};
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#define WS16C48_NGPIO_PER_REG 8
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#define WS16C48_REGMAP_IRQ(_id) \
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[_id] = { \
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.reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
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.mask = BIT((_id) % WS16C48_NGPIO_PER_REG), \
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.type = { \
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.type_reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
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.types_supported = IRQ_TYPE_EDGE_BOTH, \
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}, \
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}
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/* Only the first 24 lines (Port 0-2) support interrupts */
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#define WS16C48_NUM_IRQS 24
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static const struct regmap_irq ws16c48_regmap_irqs[WS16C48_NUM_IRQS] = {
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WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
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WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
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WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
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WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
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WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
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WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /* 15-17 */
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WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /* 18-20 */
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WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /* 21-23 */
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};
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/**
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* struct ws16c48_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @map: regmap for the device
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* @lock: synchronization lock to prevent I/O race conditions
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* @irq_mask: I/O bits affected by interrupts
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* @flow_mask: IRQ flow type mask for the respective I/O bits
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* @reg: I/O address offset for the device registers
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*/
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struct ws16c48_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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struct regmap *map;
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raw_spinlock_t lock;
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unsigned long irq_mask;
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unsigned long flow_mask;
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struct ws16c48_reg __iomem *reg;
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u8 irq_mask[WS16C48_NUM_IRQS / WS16C48_NGPIO_PER_REG];
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};
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static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws16c48gpio->lock)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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if (ws16c48gpio->io_state[port] & mask)
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return GPIO_LINE_DIRECTION_IN;
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return GPIO_LINE_DIRECTION_OUT;
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}
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static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->io_state[port] |= mask;
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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/* Lock to prevent Page/Lock register change while we handle IRQ */
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raw_spin_lock(&ws16c48gpio->lock);
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return 0;
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}
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static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&ws16c48gpio->lock)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->io_state[port] &= ~mask;
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if (value)
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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raw_spin_unlock(&ws16c48gpio->lock);
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return 0;
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}
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static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
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static int ws16c48_handle_mask_sync(const int index, const unsigned int mask_buf_def,
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const unsigned int mask_buf, void *const irq_drv_data)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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unsigned long flags;
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unsigned port_state;
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int ret = 0;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(ws16c48gpio->io_state[port] & mask)) {
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return -EINVAL;
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}
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/* exit early if no change since the last mask sync */
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if (mask_buf == ws16c48gpio->irq_mask[index])
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goto exit_unlock;
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ws16c48gpio->irq_mask[index] = mask_buf;
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port_state = ioread8(ws16c48gpio->reg->port + port);
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ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE);
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if (ret)
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goto exit_unlock;
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/* Update ENAB register (inverted mask) */
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ret = regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf);
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if (ret)
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goto exit_unlock;
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ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
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if (ret)
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goto exit_unlock;
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exit_unlock:
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return !!(port_state & mask);
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return ret;
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}
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static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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static int ws16c48_set_type_config(unsigned int **const buf, const unsigned int type,
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const struct regmap_irq *const irq_data, const int idx,
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void *const irq_drv_data)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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u8 __iomem *port_addr;
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unsigned long port_state;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
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index = offset / 8;
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port_addr = ws16c48gpio->reg->port + index;
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port_state = ioread8(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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return 0;
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}
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static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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unsigned int polarity;
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unsigned long flags;
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int ret;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* ensure that GPIO is set for output */
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if (ws16c48gpio->io_state[port] & mask) {
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return;
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}
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if (value)
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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size_t index;
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u8 __iomem *port_addr;
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unsigned long bitmask;
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unsigned long flags;
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for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
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index = offset / 8;
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port_addr = ws16c48gpio->reg->port + index;
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/* mask out GPIO configured for input */
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gpio_mask &= ~ws16c48gpio->io_state[index];
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* update output state data and set device gpio register */
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ws16c48gpio->out_state[index] &= ~gpio_mask;
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ws16c48gpio->out_state[index] |= bitmask;
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iowrite8(ws16c48gpio->out_state[index], port_addr);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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}
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static void ws16c48_irq_ack(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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unsigned port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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port_state = ws16c48gpio->irq_mask >> (8*port);
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/* Select Register Page 2; Unlock all I/O ports */
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iowrite8(0x80, &ws16c48gpio->reg->page_lock);
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/* Clear pending interrupt */
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iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
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iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port);
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/* Select Register Page 3; Unlock all I/O ports */
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iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_irq_mask(struct irq_data *data)
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{
|
||||
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
|
||||
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
|
||||
const unsigned long offset = irqd_to_hwirq(data);
|
||||
const unsigned long mask = BIT(offset);
|
||||
const unsigned port = offset / 8;
|
||||
unsigned long flags;
|
||||
unsigned long port_state;
|
||||
|
||||
/* only the first 3 ports support interrupts */
|
||||
if (port > 2)
|
||||
return;
|
||||
|
||||
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
|
||||
|
||||
ws16c48gpio->irq_mask &= ~mask;
|
||||
gpiochip_disable_irq(chip, offset);
|
||||
port_state = ws16c48gpio->irq_mask >> (8 * port);
|
||||
|
||||
/* Select Register Page 2; Unlock all I/O ports */
|
||||
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
|
||||
|
||||
/* Disable interrupt */
|
||||
iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
|
||||
|
||||
/* Select Register Page 3; Unlock all I/O ports */
|
||||
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
|
||||
|
||||
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
|
||||
}
|
||||
|
||||
static void ws16c48_irq_unmask(struct irq_data *data)
|
||||
{
|
||||
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
|
||||
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
|
||||
const unsigned long offset = irqd_to_hwirq(data);
|
||||
const unsigned long mask = BIT(offset);
|
||||
const unsigned port = offset / 8;
|
||||
unsigned long flags;
|
||||
unsigned long port_state;
|
||||
|
||||
/* only the first 3 ports support interrupts */
|
||||
if (port > 2)
|
||||
return;
|
||||
|
||||
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
|
||||
|
||||
gpiochip_enable_irq(chip, offset);
|
||||
ws16c48gpio->irq_mask |= mask;
|
||||
port_state = ws16c48gpio->irq_mask >> (8 * port);
|
||||
|
||||
/* Select Register Page 2; Unlock all I/O ports */
|
||||
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
|
||||
|
||||
/* Enable interrupt */
|
||||
iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
|
||||
|
||||
/* Select Register Page 3; Unlock all I/O ports */
|
||||
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
|
||||
|
||||
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
|
||||
}
|
||||
|
||||
static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
|
||||
{
|
||||
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
|
||||
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
|
||||
const unsigned long offset = irqd_to_hwirq(data);
|
||||
const unsigned long mask = BIT(offset);
|
||||
const unsigned port = offset / 8;
|
||||
unsigned long flags;
|
||||
unsigned long port_state;
|
||||
|
||||
/* only the first 3 ports support interrupts */
|
||||
if (port > 2)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
|
||||
|
||||
switch (flow_type) {
|
||||
case IRQ_TYPE_NONE:
|
||||
break;
|
||||
switch (type) {
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
ws16c48gpio->flow_mask |= mask;
|
||||
polarity = irq_data->mask;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
ws16c48gpio->flow_mask &= ~mask;
|
||||
polarity = 0;
|
||||
break;
|
||||
default:
|
||||
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
port_state = ws16c48gpio->flow_mask >> (8 * port);
|
||||
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
|
||||
|
||||
/* Select Register Page 1; Unlock all I/O ports */
|
||||
iowrite8(0x40, &ws16c48gpio->reg->page_lock);
|
||||
ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE);
|
||||
if (ret)
|
||||
goto exit_unlock;
|
||||
|
||||
/* Set interrupt polarity */
|
||||
iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
|
||||
ret = regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data->mask, polarity);
|
||||
if (ret)
|
||||
goto exit_unlock;
|
||||
|
||||
/* Select Register Page 3; Unlock all I/O ports */
|
||||
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
|
||||
ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
|
||||
if (ret)
|
||||
goto exit_unlock;
|
||||
|
||||
exit_unlock:
|
||||
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_chip ws16c48_irqchip = {
|
||||
.name = "ws16c48",
|
||||
.irq_ack = ws16c48_irq_ack,
|
||||
.irq_mask = ws16c48_irq_mask,
|
||||
.irq_unmask = ws16c48_irq_unmask,
|
||||
.irq_set_type = ws16c48_irq_set_type,
|
||||
.flags = IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct ws16c48_gpio *const ws16c48gpio = dev_id;
|
||||
struct gpio_chip *const chip = &ws16c48gpio->chip;
|
||||
struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
|
||||
unsigned long int_pending;
|
||||
unsigned long port;
|
||||
unsigned long int_id;
|
||||
unsigned long gpio;
|
||||
|
||||
int_pending = ioread8(®->int_pending) & 0x7;
|
||||
if (!int_pending)
|
||||
return IRQ_NONE;
|
||||
|
||||
/* loop until all pending interrupts are handled */
|
||||
do {
|
||||
for_each_set_bit(port, &int_pending, 3) {
|
||||
int_id = ioread8(reg->pol_enab_int_id + port);
|
||||
for_each_set_bit(gpio, &int_id, 8)
|
||||
generic_handle_domain_irq(chip->irq.domain,
|
||||
gpio + 8*port);
|
||||
}
|
||||
|
||||
int_pending = ioread8(®->int_pending) & 0x7;
|
||||
} while (int_pending);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define WS16C48_NGPIO 48
|
||||
@ -414,30 +220,37 @@ static const char *ws16c48_names[WS16C48_NGPIO] = {
|
||||
"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
|
||||
};
|
||||
|
||||
static int ws16c48_irq_init_hw(struct gpio_chip *gc)
|
||||
static int ws16c48_irq_init_hw(struct regmap *const map)
|
||||
{
|
||||
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
|
||||
int err;
|
||||
|
||||
/* Select Register Page 2; Unlock all I/O ports */
|
||||
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
|
||||
err = regmap_write(map, WS16C48_PAGE_LOCK, ENAB_PAGE);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Disable interrupts for all lines */
|
||||
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
|
||||
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
|
||||
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);
|
||||
err = regmap_write(map, WS16C48_ENAB + 0, 0x00);
|
||||
if (err)
|
||||
return err;
|
||||
err = regmap_write(map, WS16C48_ENAB + 1, 0x00);
|
||||
if (err)
|
||||
return err;
|
||||
err = regmap_write(map, WS16C48_ENAB + 2, 0x00);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Select Register Page 3; Unlock all I/O ports */
|
||||
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
|
||||
|
||||
return 0;
|
||||
return regmap_write(map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
|
||||
}
|
||||
|
||||
static int ws16c48_probe(struct device *dev, unsigned int id)
|
||||
{
|
||||
struct ws16c48_gpio *ws16c48gpio;
|
||||
const char *const name = dev_name(dev);
|
||||
struct gpio_irq_chip *girq;
|
||||
int err;
|
||||
struct gpio_regmap_config gpio_config = {};
|
||||
void __iomem *regs;
|
||||
struct regmap_irq_chip *chip;
|
||||
struct regmap_irq_chip_data *chip_data;
|
||||
|
||||
ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
|
||||
if (!ws16c48gpio)
|
||||
@ -449,50 +262,55 @@ static int ws16c48_probe(struct device *dev, unsigned int id)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
|
||||
if (!ws16c48gpio->reg)
|
||||
regs = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
|
||||
if (!regs)
|
||||
return -ENOMEM;
|
||||
|
||||
ws16c48gpio->chip.label = name;
|
||||
ws16c48gpio->chip.parent = dev;
|
||||
ws16c48gpio->chip.owner = THIS_MODULE;
|
||||
ws16c48gpio->chip.base = -1;
|
||||
ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
|
||||
ws16c48gpio->chip.names = ws16c48_names;
|
||||
ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
|
||||
ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
|
||||
ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
|
||||
ws16c48gpio->chip.get = ws16c48_gpio_get;
|
||||
ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
|
||||
ws16c48gpio->chip.set = ws16c48_gpio_set;
|
||||
ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
|
||||
ws16c48gpio->map = devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_config);
|
||||
if (IS_ERR(ws16c48gpio->map))
|
||||
return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map),
|
||||
"Unable to initialize register map\n");
|
||||
|
||||
girq = &ws16c48gpio->chip.irq;
|
||||
gpio_irq_chip_set_chip(girq, &ws16c48_irqchip);
|
||||
/* This will let us handle the parent IRQ in the driver */
|
||||
girq->parent_handler = NULL;
|
||||
girq->num_parents = 0;
|
||||
girq->parents = NULL;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_edge_irq;
|
||||
girq->init_hw = ws16c48_irq_init_hw;
|
||||
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->name = name;
|
||||
chip->status_base = WS16C48_INT_ID;
|
||||
chip->mask_base = WS16C48_ENAB;
|
||||
chip->ack_base = WS16C48_INT_ID;
|
||||
chip->num_regs = 3;
|
||||
chip->irqs = ws16c48_regmap_irqs;
|
||||
chip->num_irqs = ARRAY_SIZE(ws16c48_regmap_irqs);
|
||||
chip->handle_pre_irq = ws16c48_handle_pre_irq;
|
||||
chip->handle_post_irq = ws16c48_handle_post_irq;
|
||||
chip->handle_mask_sync = ws16c48_handle_mask_sync;
|
||||
chip->set_type_config = ws16c48_set_type_config;
|
||||
chip->irq_drv_data = ws16c48gpio;
|
||||
|
||||
raw_spin_lock_init(&ws16c48gpio->lock);
|
||||
|
||||
err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
|
||||
if (err) {
|
||||
dev_err(dev, "GPIO registering failed (%d)\n", err);
|
||||
/* Initialize to prevent spurious interrupts before we're ready */
|
||||
err = ws16c48_irq_init_hw(ws16c48gpio->map);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
|
||||
name, ws16c48gpio);
|
||||
if (err) {
|
||||
dev_err(dev, "IRQ handler registering failed (%d)\n", err);
|
||||
return err;
|
||||
}
|
||||
err = devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, chip, &chip_data);
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "IRQ registration failed\n");
|
||||
|
||||
return 0;
|
||||
gpio_config.parent = dev;
|
||||
gpio_config.regmap = ws16c48gpio->map;
|
||||
gpio_config.ngpio = WS16C48_NGPIO;
|
||||
gpio_config.names = ws16c48_names;
|
||||
gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
|
||||
gpio_config.reg_set_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
|
||||
/* Setting a GPIO to 0 allows it to be used as an input */
|
||||
gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
|
||||
gpio_config.ngpio_per_reg = WS16C48_NGPIO_PER_REG;
|
||||
gpio_config.irq_domain = regmap_irq_get_domain(chip_data);
|
||||
|
||||
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
|
||||
}
|
||||
|
||||
static struct isa_driver ws16c48_driver = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user