pinctrl: renesas: r8a779g0: FIX PWM suffixes
[ Upstream commit 0aabdc9a4d3644fd57d804b283b2ab0f9c28dc6c ]
PWM channels 0, 2, 8, and 9 do not have alternate pins.
Remove their "_a" or "_b" suffixes to increase uniformity.
Fixes: c606c2fde2330547 ("pinctrl: renesas: r8a779g0: Add missing PWM")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/abb748e6e1e4e7d78beac7d96e7a0a3481b32e75.1717754960.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Geert Uytterhoeven
Greg Kroah-Hartman
parent
bd0cf964b4
commit
09ed841dce
@ -310,9 +310,9 @@
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#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -349,7 +349,7 @@
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#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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@ -821,15 +821,15 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
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PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
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PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
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PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
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/* IP2SR1 */
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PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
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@ -931,7 +931,7 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
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PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
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PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
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PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
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PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
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PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
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@ -2066,13 +2066,13 @@ static const unsigned int pcie1_clkreq_n_mux[] = {
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PCIE1_CLKREQ_N_MARK,
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};
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/* - PWM0_A ------------------------------------------------------------------- */
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static const unsigned int pwm0_a_pins[] = {
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/* PWM0_A */
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/* - PWM0 ------------------------------------------------------------------- */
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static const unsigned int pwm0_pins[] = {
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/* PWM0 */
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RCAR_GP_PIN(1, 15),
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};
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static const unsigned int pwm0_a_mux[] = {
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PWM0_A_MARK,
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static const unsigned int pwm0_mux[] = {
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PWM0_MARK,
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};
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/* - PWM1_A ------------------------------------------------------------------- */
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@ -2093,13 +2093,13 @@ static const unsigned int pwm1_b_mux[] = {
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PWM1_B_MARK,
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};
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/* - PWM2_B ------------------------------------------------------------------- */
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static const unsigned int pwm2_b_pins[] = {
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/* PWM2_B */
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/* - PWM2 ------------------------------------------------------------------- */
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static const unsigned int pwm2_pins[] = {
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/* PWM2 */
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RCAR_GP_PIN(2, 14),
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};
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static const unsigned int pwm2_b_mux[] = {
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PWM2_B_MARK,
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static const unsigned int pwm2_mux[] = {
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PWM2_MARK,
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};
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/* - PWM3_A ------------------------------------------------------------------- */
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@ -2156,22 +2156,22 @@ static const unsigned int pwm7_mux[] = {
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PWM7_MARK,
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};
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/* - PWM8_A ------------------------------------------------------------------- */
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static const unsigned int pwm8_a_pins[] = {
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/* PWM8_A */
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/* - PWM8 ------------------------------------------------------------------- */
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static const unsigned int pwm8_pins[] = {
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/* PWM8 */
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RCAR_GP_PIN(1, 13),
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};
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static const unsigned int pwm8_a_mux[] = {
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PWM8_A_MARK,
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static const unsigned int pwm8_mux[] = {
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PWM8_MARK,
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};
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/* - PWM9_A ------------------------------------------------------------------- */
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static const unsigned int pwm9_a_pins[] = {
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/* PWM9_A */
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/* - PWM9 ------------------------------------------------------------------- */
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static const unsigned int pwm9_pins[] = {
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/* PWM9 */
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RCAR_GP_PIN(1, 14),
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};
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static const unsigned int pwm9_a_mux[] = {
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PWM9_A_MARK,
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static const unsigned int pwm9_mux[] = {
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PWM9_MARK,
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};
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/* - QSPI0 ------------------------------------------------------------------ */
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@ -2631,18 +2631,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(pcie0_clkreq_n),
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SH_PFC_PIN_GROUP(pcie1_clkreq_n),
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SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(pwm0),
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SH_PFC_PIN_GROUP(pwm1_a),
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SH_PFC_PIN_GROUP(pwm1_b),
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SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */
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SH_PFC_PIN_GROUP(pwm2),
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SH_PFC_PIN_GROUP(pwm3_a),
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SH_PFC_PIN_GROUP(pwm3_b),
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SH_PFC_PIN_GROUP(pwm4),
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SH_PFC_PIN_GROUP(pwm5),
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SH_PFC_PIN_GROUP(pwm6),
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SH_PFC_PIN_GROUP(pwm7),
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SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */
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SH_PFC_PIN_GROUP(pwm8),
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SH_PFC_PIN_GROUP(pwm9),
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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BUS_DATA_PIN_GROUP(qspi0_data, 2),
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@ -2891,8 +2891,7 @@ static const char * const pcie_groups[] = {
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};
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static const char * const pwm0_groups[] = {
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/* suffix might be updated */
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"pwm0_a",
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"pwm0",
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};
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static const char * const pwm1_groups[] = {
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@ -2901,8 +2900,7 @@ static const char * const pwm1_groups[] = {
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};
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static const char * const pwm2_groups[] = {
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/* suffix might be updated */
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"pwm2_b",
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"pwm2",
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};
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static const char * const pwm3_groups[] = {
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@ -2927,13 +2925,11 @@ static const char * const pwm7_groups[] = {
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};
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static const char * const pwm8_groups[] = {
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/* suffix might be updated */
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"pwm8_a",
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"pwm8",
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};
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static const char * const pwm9_groups[] = {
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/* suffix might be updated */
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"pwm9_a",
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"pwm9",
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};
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static const char * const qspi0_groups[] = {
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