arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores
This patch adds definitions for L2 cache for the Cortex-A53 CPU cores (512 KiB in size, organized as 32 KiB x 16 ways), adds Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57 + 4 x Cortex-A53), and finally enables the performance monitor unit for the Cortex-A53 cores on the R8A774A1 SoC. Based on work done for r8a7796 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -79,12 +79,59 @@
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clocks =<&cpg CPG_CORE 0>;
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};
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a53_0: cpu@100 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x100>;
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device_type = "cpu";
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power-domains = <&sysc 5>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE 1>;
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};
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a53_1: cpu@101 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x101>;
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device_type = "cpu";
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power-domains = <&sysc 6>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE 1>;
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};
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a53_2: cpu@102 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x102>;
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device_type = "cpu";
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power-domains = <&sysc 7>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE 1>;
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};
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a53_3: cpu@103 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x103>;
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device_type = "cpu";
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power-domains = <&sysc 8>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE 1>;
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};
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L2_CA57: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc 12>;
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cache-unified;
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cache-level = <2>;
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};
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L2_CA53: cache-controller-1 {
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compatible = "cache";
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power-domains = <&sysc 21>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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@ -108,6 +155,15 @@
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clock-frequency = <0>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
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};
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pmu_a57 {
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compatible = "arm,cortex-a57-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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@ -977,7 +1033,7 @@
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc 32>;
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@ -1037,10 +1093,10 @@
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/* External USB clocks - can be overridden by the board */
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