drm/i915: Limit the display memory alignment to 32 bit instead of 64
The coming commit "drm/i915: Introduce guard pages to i915_vma" from Chris, was originally changing display_alignment to u32 from u64. The reason is that the display GGTT is and will be limited o 4GB. Put it in a separate patch and use "max(...)" instead of "max_t(64, ...)" when asigning the value. We can safely use max as we know beforehand that the comparison is between two u32 variables. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221130235805.221010-2-andi.shyti@linux.intel.com
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@ -91,7 +91,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
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goto err;
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}
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vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
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vma->display_alignment = max(vma->display_alignment, alignment);
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i915_gem_object_flush_if_display(obj);
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@ -444,7 +444,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
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if (IS_ERR(vma))
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return vma;
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vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
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vma->display_alignment = max(vma->display_alignment, alignment);
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i915_vma_mark_scanout(vma);
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i915_gem_object_flush_if_display_locked(obj);
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@ -197,7 +197,6 @@ struct i915_vma {
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struct i915_fence_reg *fence;
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u64 size;
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u64 display_alignment;
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struct i915_page_sizes page_sizes;
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/* mmap-offset associated with fencing for this vma */
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@ -205,6 +204,7 @@ struct i915_vma {
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u32 fence_size;
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u32 fence_alignment;
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u32 display_alignment;
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/**
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* Count of the number of times this vma has been opened by different
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