drm/radeon: create radeon_asic.c
And move asic init plus a few related functions from radeon_device.c to it. This file will hold all the asic structures in the future, but atm they're still stuck in radeon_asic.h. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
1fc59eda33
commit
0a10c85129
@ -50,7 +50,7 @@ $(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
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radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
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radeon_irq.o r300_cmdbuf.o r600_cp.o
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# add KMS driver
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radeon-y += radeon_device.o radeon_kms.o \
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radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
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atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
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radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \
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@ -863,6 +863,12 @@ union radeon_asic_config {
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struct rv770_asic rv770;
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};
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/*
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* asic initizalization from radeon_asic.c
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*/
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void radeon_agp_disable(struct radeon_device *rdev);
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int radeon_asic_init(struct radeon_device *rdev);
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/*
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* IOCTL.
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236
drivers/gpu/drm/radeon/radeon_asic.c
Normal file
236
drivers/gpu/drm/radeon/radeon_asic.c
Normal file
@ -0,0 +1,236 @@
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/console.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "atom.h"
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/*
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* Registers accessors functions.
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*/
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static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
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BUG_ON(1);
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return 0;
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}
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static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
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reg, v);
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BUG_ON(1);
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}
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static void radeon_register_accessor_init(struct radeon_device *rdev)
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{
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rdev->mc_rreg = &radeon_invalid_rreg;
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rdev->mc_wreg = &radeon_invalid_wreg;
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rdev->pll_rreg = &radeon_invalid_rreg;
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rdev->pll_wreg = &radeon_invalid_wreg;
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rdev->pciep_rreg = &radeon_invalid_rreg;
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rdev->pciep_wreg = &radeon_invalid_wreg;
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/* Don't change order as we are overridding accessor. */
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if (rdev->family < CHIP_RV515) {
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rdev->pcie_reg_mask = 0xff;
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} else {
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rdev->pcie_reg_mask = 0x7ff;
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}
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/* FIXME: not sure here */
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if (rdev->family <= CHIP_R580) {
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rdev->pll_rreg = &r100_pll_rreg;
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rdev->pll_wreg = &r100_pll_wreg;
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}
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if (rdev->family >= CHIP_R420) {
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rdev->mc_rreg = &r420_mc_rreg;
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rdev->mc_wreg = &r420_mc_wreg;
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}
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if (rdev->family >= CHIP_RV515) {
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rdev->mc_rreg = &rv515_mc_rreg;
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rdev->mc_wreg = &rv515_mc_wreg;
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}
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
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rdev->mc_rreg = &rs400_mc_rreg;
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rdev->mc_wreg = &rs400_mc_wreg;
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}
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if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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rdev->mc_rreg = &rs690_mc_rreg;
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rdev->mc_wreg = &rs690_mc_wreg;
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}
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if (rdev->family == CHIP_RS600) {
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rdev->mc_rreg = &rs600_mc_rreg;
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rdev->mc_wreg = &rs600_mc_wreg;
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}
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if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
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rdev->pciep_rreg = &r600_pciep_rreg;
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rdev->pciep_wreg = &r600_pciep_wreg;
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}
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}
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/* helper to disable agp */
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void radeon_agp_disable(struct radeon_device *rdev)
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{
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rdev->flags &= ~RADEON_IS_AGP;
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if (rdev->family >= CHIP_R600) {
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DRM_INFO("Forcing AGP to PCIE mode\n");
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rdev->flags |= RADEON_IS_PCIE;
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} else if (rdev->family >= CHIP_RV515 ||
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rdev->family == CHIP_RV380 ||
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rdev->family == CHIP_RV410 ||
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rdev->family == CHIP_R423) {
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DRM_INFO("Forcing AGP to PCIE mode\n");
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rdev->flags |= RADEON_IS_PCIE;
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rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
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rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
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} else {
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DRM_INFO("Forcing AGP to PCI mode\n");
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rdev->flags |= RADEON_IS_PCI;
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rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
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rdev->asic->gart_set_page = &r100_pci_gart_set_page;
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}
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rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
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}
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/*
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* ASIC
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*/
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int radeon_asic_init(struct radeon_device *rdev)
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{
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radeon_register_accessor_init(rdev);
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switch (rdev->family) {
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case CHIP_R100:
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case CHIP_RV100:
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case CHIP_RS100:
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case CHIP_RV200:
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case CHIP_RS200:
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rdev->asic = &r100_asic;
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break;
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case CHIP_R200:
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case CHIP_RV250:
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case CHIP_RS300:
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case CHIP_RV280:
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rdev->asic = &r200_asic;
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break;
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_RV350:
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case CHIP_RV380:
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if (rdev->flags & RADEON_IS_PCIE)
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rdev->asic = &r300_asic_pcie;
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else
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rdev->asic = &r300_asic;
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break;
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case CHIP_R420:
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case CHIP_R423:
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case CHIP_RV410:
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rdev->asic = &r420_asic;
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break;
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case CHIP_RS400:
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case CHIP_RS480:
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rdev->asic = &rs400_asic;
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break;
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case CHIP_RS600:
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rdev->asic = &rs600_asic;
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break;
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case CHIP_RS690:
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case CHIP_RS740:
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rdev->asic = &rs690_asic;
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break;
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case CHIP_RV515:
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rdev->asic = &rv515_asic;
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break;
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case CHIP_R520:
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case CHIP_RV530:
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case CHIP_RV560:
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case CHIP_RV570:
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case CHIP_R580:
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rdev->asic = &r520_asic;
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break;
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case CHIP_R600:
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case CHIP_RV610:
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case CHIP_RV630:
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case CHIP_RV620:
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case CHIP_RV635:
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case CHIP_RV670:
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case CHIP_RS780:
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case CHIP_RS880:
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rdev->asic = &r600_asic;
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break;
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case CHIP_RV770:
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case CHIP_RV730:
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case CHIP_RV710:
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case CHIP_RV740:
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rdev->asic = &rv770_asic;
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break;
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case CHIP_CEDAR:
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case CHIP_REDWOOD:
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case CHIP_JUNIPER:
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case CHIP_CYPRESS:
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case CHIP_HEMLOCK:
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rdev->asic = &evergreen_asic;
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break;
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default:
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/* FIXME: not supported yet */
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return -EINVAL;
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}
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if (rdev->flags & RADEON_IS_IGP) {
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rdev->asic->get_memory_clock = NULL;
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rdev->asic->set_memory_clock = NULL;
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}
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return 0;
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}
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/*
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* Wrapper around modesetting bits. Move to radeon_clocks.c?
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*/
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int radeon_clocks_init(struct radeon_device *rdev)
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{
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int r;
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r = radeon_static_clocks_init(rdev->ddev);
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if (r) {
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return r;
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}
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DRM_INFO("Clocks initialized !\n");
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return 0;
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}
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void radeon_clocks_fini(struct radeon_device *rdev)
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{
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}
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@ -33,7 +33,6 @@
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#include <linux/vga_switcheroo.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "atom.h"
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/*
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@ -288,181 +287,6 @@ void radeon_dummy_page_fini(struct radeon_device *rdev)
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}
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/*
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* Registers accessors functions.
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*/
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uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
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BUG_ON(1);
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return 0;
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}
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void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
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reg, v);
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BUG_ON(1);
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}
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void radeon_register_accessor_init(struct radeon_device *rdev)
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{
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rdev->mc_rreg = &radeon_invalid_rreg;
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rdev->mc_wreg = &radeon_invalid_wreg;
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rdev->pll_rreg = &radeon_invalid_rreg;
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rdev->pll_wreg = &radeon_invalid_wreg;
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rdev->pciep_rreg = &radeon_invalid_rreg;
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rdev->pciep_wreg = &radeon_invalid_wreg;
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/* Don't change order as we are overridding accessor. */
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if (rdev->family < CHIP_RV515) {
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rdev->pcie_reg_mask = 0xff;
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} else {
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rdev->pcie_reg_mask = 0x7ff;
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}
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/* FIXME: not sure here */
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if (rdev->family <= CHIP_R580) {
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rdev->pll_rreg = &r100_pll_rreg;
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rdev->pll_wreg = &r100_pll_wreg;
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}
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if (rdev->family >= CHIP_R420) {
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rdev->mc_rreg = &r420_mc_rreg;
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rdev->mc_wreg = &r420_mc_wreg;
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}
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if (rdev->family >= CHIP_RV515) {
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rdev->mc_rreg = &rv515_mc_rreg;
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rdev->mc_wreg = &rv515_mc_wreg;
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}
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
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rdev->mc_rreg = &rs400_mc_rreg;
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rdev->mc_wreg = &rs400_mc_wreg;
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}
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if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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rdev->mc_rreg = &rs690_mc_rreg;
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rdev->mc_wreg = &rs690_mc_wreg;
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}
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if (rdev->family == CHIP_RS600) {
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rdev->mc_rreg = &rs600_mc_rreg;
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rdev->mc_wreg = &rs600_mc_wreg;
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}
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if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
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rdev->pciep_rreg = &r600_pciep_rreg;
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rdev->pciep_wreg = &r600_pciep_wreg;
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}
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}
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/*
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* ASIC
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*/
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int radeon_asic_init(struct radeon_device *rdev)
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{
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radeon_register_accessor_init(rdev);
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switch (rdev->family) {
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case CHIP_R100:
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case CHIP_RV100:
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case CHIP_RS100:
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case CHIP_RV200:
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case CHIP_RS200:
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rdev->asic = &r100_asic;
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break;
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case CHIP_R200:
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case CHIP_RV250:
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case CHIP_RS300:
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case CHIP_RV280:
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rdev->asic = &r200_asic;
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break;
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_RV350:
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case CHIP_RV380:
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if (rdev->flags & RADEON_IS_PCIE)
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rdev->asic = &r300_asic_pcie;
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else
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rdev->asic = &r300_asic;
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break;
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case CHIP_R420:
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case CHIP_R423:
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case CHIP_RV410:
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rdev->asic = &r420_asic;
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break;
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case CHIP_RS400:
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case CHIP_RS480:
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rdev->asic = &rs400_asic;
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break;
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case CHIP_RS600:
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rdev->asic = &rs600_asic;
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break;
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case CHIP_RS690:
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case CHIP_RS740:
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rdev->asic = &rs690_asic;
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break;
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case CHIP_RV515:
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rdev->asic = &rv515_asic;
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break;
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case CHIP_R520:
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case CHIP_RV530:
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case CHIP_RV560:
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case CHIP_RV570:
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case CHIP_R580:
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rdev->asic = &r520_asic;
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break;
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case CHIP_R600:
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case CHIP_RV610:
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case CHIP_RV630:
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case CHIP_RV620:
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case CHIP_RV635:
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case CHIP_RV670:
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case CHIP_RS780:
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case CHIP_RS880:
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rdev->asic = &r600_asic;
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break;
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case CHIP_RV770:
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case CHIP_RV730:
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case CHIP_RV710:
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case CHIP_RV740:
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rdev->asic = &rv770_asic;
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break;
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case CHIP_CEDAR:
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case CHIP_REDWOOD:
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case CHIP_JUNIPER:
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case CHIP_CYPRESS:
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case CHIP_HEMLOCK:
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rdev->asic = &evergreen_asic;
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break;
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default:
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/* FIXME: not supported yet */
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return -EINVAL;
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}
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if (rdev->flags & RADEON_IS_IGP) {
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rdev->asic->get_memory_clock = NULL;
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rdev->asic->set_memory_clock = NULL;
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}
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return 0;
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}
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/*
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* Wrapper around modesetting bits.
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*/
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int radeon_clocks_init(struct radeon_device *rdev)
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{
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int r;
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r = radeon_static_clocks_init(rdev->ddev);
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if (r) {
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return r;
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}
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DRM_INFO("Clocks initialized !\n");
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return 0;
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}
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void radeon_clocks_fini(struct radeon_device *rdev)
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{
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}
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/* ATOM accessor methods */
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static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
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{
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@ -567,29 +391,6 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state)
|
||||
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
||||
}
|
||||
|
||||
void radeon_agp_disable(struct radeon_device *rdev)
|
||||
{
|
||||
rdev->flags &= ~RADEON_IS_AGP;
|
||||
if (rdev->family >= CHIP_R600) {
|
||||
DRM_INFO("Forcing AGP to PCIE mode\n");
|
||||
rdev->flags |= RADEON_IS_PCIE;
|
||||
} else if (rdev->family >= CHIP_RV515 ||
|
||||
rdev->family == CHIP_RV380 ||
|
||||
rdev->family == CHIP_RV410 ||
|
||||
rdev->family == CHIP_R423) {
|
||||
DRM_INFO("Forcing AGP to PCIE mode\n");
|
||||
rdev->flags |= RADEON_IS_PCIE;
|
||||
rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
|
||||
rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
|
||||
} else {
|
||||
DRM_INFO("Forcing AGP to PCI mode\n");
|
||||
rdev->flags |= RADEON_IS_PCI;
|
||||
rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
|
||||
rdev->asic->gart_set_page = &r100_pci_gart_set_page;
|
||||
}
|
||||
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
||||
}
|
||||
|
||||
void radeon_check_arguments(struct radeon_device *rdev)
|
||||
{
|
||||
/* vramlimit must be a power of two */
|
||||
|
Loading…
Reference in New Issue
Block a user