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arm64: dts: Add L2 cache node to msm8916

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The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Stephen Boyd 2016-01-08 15:57:09 -08:00 committed by Andy Gross
parent 886c73babe
commit 0a9bcf4e09
1 changed files with 9 additions and 0 deletions
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9
arch/arm64/boot/dts/qcom/msm8916.dtsi
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@ -61,24 +61,33 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
next-level-cache = <&L2_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x1>;
next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x2>;
next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x3>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};