Power management fix for 5.3-rc4
Revert a recent PCI power management change that caused problems to occur on multiple systems (Mika Westerberg). -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEE4fcc61cGeeHD/fCwgsRv/nhiVHEFAl1NMCUSHHJqd0Byand5 c29ja2kubmV0AAoJEILEb/54YlRx3uwP/0xPSXXVGD5ypOT4xPD6yP8otbZNAGSL X2sUygXFptVdbAa5+Lkzr6t1XL/TxeB3mQHIPjYGqoMwJ0byVAmc54EQxc+5hyqF fPBOBGSrTiTSCXdr4o3f9ptD9CKUwz/u/qzKYP/uJYogzLeA9b+EQxkhWnWppD2L nW4KYN/X2+Mwn7591JSfATVFI0u97jkeCY1vXNYZFv1jcKQ3XVMs1Tyujge4Wz3J 9ix04RqHvfkDHO3FHhuHkxyBY5XtPVePqLWl3vHNt5yITAHjn3olc0J5hem/zBUQ +KwppDFC0AFxNiIai6hhO89hO0e2EMGot20F3v7CaQRDiPxQwN+t8pUzy7Bf6/fj qOTMSwBxXFH/1HCwceoLdV26GZhio+edE2a+iXEeCSpiKn+ZGJWgyHlJo7ekZYad WP2R//t8jokRzmHkPYGxVkb51xWHGtHVdEGExWWvOEseBx3rtZdDjU9aBVtVNBJc 1jimXO5cqCb3f6iwFOvI0vZBWU74NVtsKOkHQ5v8W5bxoP74Y2gP9OAzH85Cl7/a ug9BYiflPWIbbi81uY+R3y+//M1U5lgdGS/A+k4Q6siOausZ1q0FKTGgw+fpklSm B2b78l2Kr5+kerpEHzVoCxAPgo/QoHttbujMlQ7nmRsQbya45Io7WL0gUKb1hlNk 96fQbwVoQPDF =u7Zm -----END PGP SIGNATURE----- Merge tag 'pm-5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management fix from Rafael Wysocki: "Revert a recent PCI power management change that caused problems to occur on multiple systems (Mika Westerberg)" * tag 'pm-5.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: Revert "PCI: Add missing link delays required by the PCIe spec"
This commit is contained in:
Linus Torvalds
commit
0acf5676dc
@ -1025,10 +1025,15 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
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if (state == PCI_D0) {
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pci_platform_power_transition(dev, PCI_D0);
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/*
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* Mandatory power management transition delays are
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* handled in the PCIe portdrv resume hooks.
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* Mandatory power management transition delays, see
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* PCI Express Base Specification Revision 2.0 Section
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* 6.6.1: Conventional Reset. Do not delay for
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* devices powered on/off by corresponding bridge,
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* because have already delayed for the bridge.
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*/
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if (dev->runtime_d3cold) {
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if (dev->d3cold_delay && !dev->imm_ready)
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msleep(dev->d3cold_delay);
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/*
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* When powering on a bridge from D3cold, the
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* whole hierarchy may be powered on into
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@ -4602,16 +4607,14 @@ static int pci_pm_reset(struct pci_dev *dev, int probe)
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return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
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}
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/**
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* pcie_wait_for_link_delay - Wait until link is active or inactive
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* pcie_wait_for_link - Wait until link is active or inactive
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* @pdev: Bridge device
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* @active: waiting for active or inactive?
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* @delay: Delay to wait after link has become active (in ms)
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*
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* Use this to wait till link becomes active or inactive.
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*/
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bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay)
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bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
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{
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int timeout = 1000;
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bool ret;
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@ -4648,25 +4651,13 @@ bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay)
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timeout -= 10;
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}
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if (active && ret)
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msleep(delay);
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msleep(100);
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else if (ret != active)
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pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
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active ? "set" : "cleared");
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return ret == active;
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}
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/**
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* pcie_wait_for_link - Wait until link is active or inactive
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* @pdev: Bridge device
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* @active: waiting for active or inactive?
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*
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* Use this to wait till link becomes active or inactive.
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*/
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bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
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{
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return pcie_wait_for_link_delay(pdev, active, 100);
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}
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void pci_reset_secondary_bus(struct pci_dev *dev)
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{
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u16 ctrl;
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@ -497,7 +497,6 @@ static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
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void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
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u32 service);
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bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay);
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bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
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#ifdef CONFIG_PCIEASPM
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void pcie_aspm_init_link_state(struct pci_dev *pdev);
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@ -9,7 +9,6 @@
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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@ -379,67 +378,6 @@ static int pm_iter(struct device *dev, void *data)
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return 0;
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}
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static int get_downstream_delay(struct pci_bus *bus)
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{
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struct pci_dev *pdev;
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int min_delay = 100;
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int max_delay = 0;
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list_for_each_entry(pdev, &bus->devices, bus_list) {
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if (!pdev->imm_ready)
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min_delay = 0;
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else if (pdev->d3cold_delay < min_delay)
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min_delay = pdev->d3cold_delay;
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if (pdev->d3cold_delay > max_delay)
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max_delay = pdev->d3cold_delay;
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}
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return max(min_delay, max_delay);
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}
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/*
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* wait_for_downstream_link - Wait for downstream link to establish
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* @pdev: PCIe port whose downstream link is waited
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*
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* Handle delays according to PCIe 4.0 section 6.6.1 before configuration
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* access to the downstream component is permitted.
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*
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* This blocks PCI core resume of the hierarchy below this port until the
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* link is trained. Should be called before resuming port services to
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* prevent pciehp from starting to tear-down the hierarchy too soon.
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*/
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static void wait_for_downstream_link(struct pci_dev *pdev)
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{
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int delay;
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if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
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pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
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return;
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if (pci_dev_is_disconnected(pdev))
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return;
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if (!pdev->subordinate || list_empty(&pdev->subordinate->devices) ||
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!pdev->bridge_d3)
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return;
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delay = get_downstream_delay(pdev->subordinate);
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if (!delay)
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return;
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dev_dbg(&pdev->dev, "waiting downstream link for %d ms\n", delay);
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/*
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* If downstream port does not support speeds greater than 5 GT/s
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* need to wait 100ms. For higher speeds (gen3) we need to wait
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* first for the data link layer to become active.
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*/
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if (pcie_get_speed_cap(pdev) <= PCIE_SPEED_5_0GT)
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msleep(delay);
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else
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pcie_wait_for_link_delay(pdev, true, delay);
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}
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/**
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* pcie_port_device_suspend - suspend port services associated with a PCIe port
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* @dev: PCI Express port to handle
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@ -453,8 +391,6 @@ int pcie_port_device_suspend(struct device *dev)
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int pcie_port_device_resume_noirq(struct device *dev)
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{
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size_t off = offsetof(struct pcie_port_service_driver, resume_noirq);
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wait_for_downstream_link(to_pci_dev(dev));
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return device_for_each_child(dev, &off, pm_iter);
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}
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@ -485,8 +421,6 @@ int pcie_port_device_runtime_suspend(struct device *dev)
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int pcie_port_device_runtime_resume(struct device *dev)
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{
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size_t off = offsetof(struct pcie_port_service_driver, runtime_resume);
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wait_for_downstream_link(to_pci_dev(dev));
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return device_for_each_child(dev, &off, pm_iter);
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}
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#endif /* PM */
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