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ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q

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This adds scu and general purpose registers device nodes required for
SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
address from general purpose (SW generic) register 1.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Tested-by: Antoine Tenart <antoine.tenart@free-electrons.com>
This commit is contained in:
Sebastian Hesselbarth 2014-03-13 13:32:34 +01:00
parent 55d3de5480
commit 0bd4b3461b
2 changed files with 20 additions and 0 deletions
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10
arch/arm/boot/dts/berlin2.dtsi
View File

@ -72,6 +72,11 @@
cache-level = <2>;
};
scu: snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x58>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
@ -176,6 +181,11 @@
};
};
generic-regs@ea0184 {
compatible = "marvell,berlin-generic-regs", "syscon";
reg = <0xea0184 0x10>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;

10
arch/arm/boot/dts/berlin2q.dtsi
View File

@ -87,6 +87,11 @@
cache-level = <2>;
};
scu: snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x58>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
@ -183,6 +188,11 @@
};
};
generic-regs@ea0110 {
compatible = "marvell,berlin-generic-regs", "syscon";
reg = <0xea0110 0x10>;
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;