ASoC: Fix FLL reference clock division setup in WM8993
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -345,8 +345,10 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
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/* Fref must be <=13.5MHz */
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div = 1;
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fll_div->fll_clk_ref_div = 0;
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while ((Fref / div) > 13500000) {
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div *= 2;
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fll_div->fll_clk_ref_div++;
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if (div > 8) {
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pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
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