Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI: OF: Don't crash when bridge parent is NULL. PCI: export pcie_bus_configure_settings symbol PCI: code and comments cleanup PCI: make cardbus-bridge resources optional PCI: make SRIOV resources optional PCI : ability to relocate assigned pci-resources PCI: honor child buses add_size in hot plug configuration PCI: Set PCI-E Max Payload Size on fabric
This commit is contained in:
Linus Torvalds
commit
0c3bef6128
@ -360,6 +360,15 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
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}
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}
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/* After the PCI-E bus has been walked and all devices discovered,
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* configure any settings of the fabric that might be necessary.
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*/
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if (bus) {
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struct pci_bus *child;
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child, child->self->pcie_mpss);
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}
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if (!bus)
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kfree(sd);
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@ -158,47 +158,6 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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*/
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}
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/* Program PCIE MaxPayload setting on device: ensure parent maxpayload <= device */
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static int pci_set_payload(struct pci_dev *dev)
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{
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int pos, ppos;
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u16 pctl, psz;
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u16 dctl, dsz, dcap, dmax;
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struct pci_dev *parent;
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parent = dev->bus->self;
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pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (!pos)
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return 0;
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/* Read Device MaxPayload capability and setting */
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &dctl);
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pci_read_config_word(dev, pos + PCI_EXP_DEVCAP, &dcap);
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dsz = (dctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
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dmax = (dcap & PCI_EXP_DEVCAP_PAYLOAD);
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/* Read Parent MaxPayload setting */
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ppos = pci_find_capability(parent, PCI_CAP_ID_EXP);
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if (!ppos)
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return 0;
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pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
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psz = (pctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
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/* If parent payload > device max payload -> error
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* If parent payload > device payload -> set speed
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* If parent payload <= device payload -> do nothing
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*/
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if (psz > dmax)
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return -1;
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else if (psz > dsz) {
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dev_info(&dev->dev, "Setting MaxPayload to %d\n", 128 << psz);
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
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(dctl & ~PCI_EXP_DEVCTL_PAYLOAD) +
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(psz << 5));
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}
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return 0;
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}
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void pci_configure_slot(struct pci_dev *dev)
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{
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struct pci_dev *cdev;
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@ -210,9 +169,7 @@ void pci_configure_slot(struct pci_dev *dev)
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
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return;
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ret = pci_set_payload(dev);
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if (ret)
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dev_warn(&dev->dev, "could not set device max payload\n");
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pcie_bus_configure_settings(dev->bus, dev->bus->self->pcie_mpss);
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memset(&hpp, 0, sizeof(hpp));
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ret = pci_get_hp_params(dev, &hpp);
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@ -55,7 +55,7 @@ struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus)
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*/
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if (bus->bridge->of_node)
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return of_node_get(bus->bridge->of_node);
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if (bus->bridge->parent->of_node)
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if (bus->bridge->parent && bus->bridge->parent->of_node)
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return of_node_get(bus->bridge->parent->of_node);
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return NULL;
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}
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@ -77,6 +77,8 @@ unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
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unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
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unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
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/*
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* The default CLS is used if arch didn't set CLS explicitly and not
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* all pci devices agree on the same value. Arch can override either
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@ -3222,6 +3224,67 @@ out:
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}
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EXPORT_SYMBOL(pcie_set_readrq);
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/**
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* pcie_get_mps - get PCI Express maximum payload size
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* @dev: PCI device to query
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*
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* Returns maximum payload size in bytes
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* or appropriate error value.
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*/
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int pcie_get_mps(struct pci_dev *dev)
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{
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int ret, cap;
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u16 ctl;
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cap = pci_pcie_cap(dev);
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if (!cap)
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return -EINVAL;
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ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
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if (!ret)
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ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
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return ret;
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}
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/**
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* pcie_set_mps - set PCI Express maximum payload size
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* @dev: PCI device to query
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* @rq: maximum payload size in bytes
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* valid values are 128, 256, 512, 1024, 2048, 4096
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*
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* If possible sets maximum payload size
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*/
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int pcie_set_mps(struct pci_dev *dev, int mps)
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{
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int cap, err = -EINVAL;
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u16 ctl, v;
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if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
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goto out;
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v = ffs(mps) - 8;
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if (v > dev->pcie_mpss)
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goto out;
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v <<= 5;
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cap = pci_pcie_cap(dev);
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if (!cap)
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goto out;
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err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
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if (err)
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goto out;
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if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
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ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
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ctl |= v;
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err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
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}
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out:
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return err;
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}
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/**
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* pci_select_bars - Make BAR mask from the type of resource
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* @dev: the PCI device for which BAR mask is made
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@ -3505,6 +3568,10 @@ static int __init pci_setup(char *str)
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pci_hotplug_io_size = memparse(str + 9, &str);
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} else if (!strncmp(str, "hpmemsize=", 10)) {
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pci_hotplug_mem_size = memparse(str + 10, &str);
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} else if (!strncmp(str, "pcie_bus_safe", 13)) {
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pcie_bus_config = PCIE_BUS_SAFE;
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} else if (!strncmp(str, "pcie_bus_perf", 13)) {
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pcie_bus_config = PCIE_BUS_PERFORMANCE;
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} else {
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printk(KERN_ERR "PCI: Unknown option `%s'\n",
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str);
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@ -283,6 +283,8 @@ static inline int pci_iov_bus_range(struct pci_bus *bus)
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#endif /* CONFIG_PCI_IOV */
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extern unsigned long pci_cardbus_resource_alignment(struct resource *);
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static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
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struct resource *res)
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{
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@ -292,6 +294,8 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
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if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
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return pci_sriov_resource_alignment(dev, resno);
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#endif
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if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
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return pci_cardbus_resource_alignment(res);
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return resource_alignment(res);
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}
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@ -856,6 +856,8 @@ void set_pcie_port_type(struct pci_dev *pdev)
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pdev->pcie_cap = pos;
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pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
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pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
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pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
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pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
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}
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void set_pcie_hotplug_bridge(struct pci_dev *pdev)
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@ -1326,6 +1328,150 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
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return nr;
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}
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static int pcie_find_smpss(struct pci_dev *dev, void *data)
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{
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u8 *smpss = data;
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if (!pci_is_pcie(dev))
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return 0;
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/* For PCIE hotplug enabled slots not connected directly to a
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* PCI-E root port, there can be problems when hotplugging
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* devices. This is due to the possibility of hotplugging a
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* device into the fabric with a smaller MPS that the devices
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* currently running have configured. Modifying the MPS on the
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* running devices could cause a fatal bus error due to an
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* incoming frame being larger than the newly configured MPS.
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* To work around this, the MPS for the entire fabric must be
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* set to the minimum size. Any devices hotplugged into this
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* fabric will have the minimum MPS set. If the PCI hotplug
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* slot is directly connected to the root port and there are not
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* other devices on the fabric (which seems to be the most
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* common case), then this is not an issue and MPS discovery
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* will occur as normal.
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*/
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if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
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dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
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*smpss = 0;
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if (*smpss > dev->pcie_mpss)
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*smpss = dev->pcie_mpss;
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return 0;
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}
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static void pcie_write_mps(struct pci_dev *dev, int mps)
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{
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int rc, dev_mpss;
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dev_mpss = 128 << dev->pcie_mpss;
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if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
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if (dev->bus->self) {
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dev_dbg(&dev->bus->dev, "Bus MPSS %d\n",
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128 << dev->bus->self->pcie_mpss);
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/* For "MPS Force Max", the assumption is made that
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* downstream communication will never be larger than
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* the MRRS. So, the MPS only needs to be configured
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* for the upstream communication. This being the case,
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* walk from the top down and set the MPS of the child
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* to that of the parent bus.
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*/
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mps = 128 << dev->bus->self->pcie_mpss;
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if (mps > dev_mpss)
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dev_warn(&dev->dev, "MPS configured higher than"
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" maximum supported by the device. If"
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" a bus issue occurs, try running with"
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" pci=pcie_bus_safe.\n");
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}
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dev->pcie_mpss = ffs(mps) - 8;
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}
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rc = pcie_set_mps(dev, mps);
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if (rc)
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dev_err(&dev->dev, "Failed attempting to set the MPS\n");
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}
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static void pcie_write_mrrs(struct pci_dev *dev, int mps)
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{
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int rc, mrrs;
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if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
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int dev_mpss = 128 << dev->pcie_mpss;
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/* For Max performance, the MRRS must be set to the largest
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* supported value. However, it cannot be configured larger
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* than the MPS the device or the bus can support. This assumes
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* that the largest MRRS available on the device cannot be
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* smaller than the device MPSS.
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*/
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mrrs = mps < dev_mpss ? mps : dev_mpss;
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} else
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/* In the "safe" case, configure the MRRS for fairness on the
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* bus by making all devices have the same size
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*/
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mrrs = mps;
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/* MRRS is a R/W register. Invalid values can be written, but a
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* subsiquent read will verify if the value is acceptable or not.
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* If the MRRS value provided is not acceptable (e.g., too large),
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* shrink the value until it is acceptable to the HW.
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*/
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while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
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rc = pcie_set_readrq(dev, mrrs);
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if (rc)
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dev_err(&dev->dev, "Failed attempting to set the MRRS\n");
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mrrs /= 2;
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}
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}
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static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
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{
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int mps = 128 << *(u8 *)data;
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if (!pci_is_pcie(dev))
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return 0;
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dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
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pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
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pcie_write_mps(dev, mps);
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pcie_write_mrrs(dev, mps);
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dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
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pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
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return 0;
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}
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/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down,
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* parents then children fashion. If this changes, then this code will not
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* work as designed.
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*/
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void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
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{
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u8 smpss = mpss;
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if (!bus->self)
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return;
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if (!pci_is_pcie(bus->self))
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return;
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if (pcie_bus_config == PCIE_BUS_SAFE) {
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pcie_find_smpss(bus->self, &smpss);
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pci_walk_bus(bus, pcie_find_smpss, &smpss);
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}
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pcie_bus_configure_set(bus->self, &smpss);
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pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
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}
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EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
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unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
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{
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unsigned int devfn, pass, max = bus->secondary;
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@ -34,6 +34,7 @@ struct resource_list_x {
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resource_size_t start;
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resource_size_t end;
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resource_size_t add_size;
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resource_size_t min_align;
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unsigned long flags;
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};
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@ -65,7 +66,7 @@ void pci_realloc(void)
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*/
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static void add_to_list(struct resource_list_x *head,
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struct pci_dev *dev, struct resource *res,
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resource_size_t add_size)
|
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resource_size_t add_size, resource_size_t min_align)
|
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{
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struct resource_list_x *list = head;
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struct resource_list_x *ln = list->next;
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@ -84,13 +85,16 @@ static void add_to_list(struct resource_list_x *head,
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tmp->end = res->end;
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tmp->flags = res->flags;
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tmp->add_size = add_size;
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tmp->min_align = min_align;
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list->next = tmp;
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}
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static void add_to_failed_list(struct resource_list_x *head,
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struct pci_dev *dev, struct resource *res)
|
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{
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add_to_list(head, dev, res, 0);
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add_to_list(head, dev, res,
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0 /* dont care */,
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0 /* dont care */);
|
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}
|
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|
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static void __dev_sort_resources(struct pci_dev *dev,
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@ -121,18 +125,18 @@ static inline void reset_resource(struct resource *res)
|
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}
|
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|
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/**
|
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* adjust_resources_sorted() - satisfy any additional resource requests
|
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* reassign_resources_sorted() - satisfy any additional resource requests
|
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*
|
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* @add_head : head of the list tracking requests requiring additional
|
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* @realloc_head : head of the list tracking requests requiring additional
|
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* resources
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* @head : head of the list tracking requests with allocated
|
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* resources
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*
|
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* Walk through each element of the add_head and try to procure
|
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* Walk through each element of the realloc_head and try to procure
|
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* additional resources for the element, provided the element
|
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* is in the head list.
|
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*/
|
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static void adjust_resources_sorted(struct resource_list_x *add_head,
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static void reassign_resources_sorted(struct resource_list_x *realloc_head,
|
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struct resource_list *head)
|
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{
|
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struct resource *res;
|
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@ -141,8 +145,8 @@ static void adjust_resources_sorted(struct resource_list_x *add_head,
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resource_size_t add_size;
|
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int idx;
|
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|
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prev = add_head;
|
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for (list = add_head->next; list;) {
|
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prev = realloc_head;
|
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for (list = realloc_head->next; list;) {
|
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res = list->res;
|
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/* skip resource that has been reset */
|
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if (!res->flags)
|
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@ -159,13 +163,17 @@ static void adjust_resources_sorted(struct resource_list_x *add_head,
|
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|
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idx = res - &list->dev->resource[0];
|
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add_size=list->add_size;
|
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if (!resource_size(res) && add_size) {
|
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if (!resource_size(res)) {
|
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res->start = list->start;
|
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res->end = res->start + add_size - 1;
|
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if(pci_assign_resource(list->dev, idx))
|
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reset_resource(res);
|
||||
} else if (add_size) {
|
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adjust_resource(res, res->start,
|
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resource_size(res) + add_size);
|
||||
} else {
|
||||
resource_size_t align = list->min_align;
|
||||
res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
|
||||
if (pci_reassign_resource(list->dev, idx, add_size, align))
|
||||
dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n",
|
||||
res);
|
||||
}
|
||||
out:
|
||||
tmp = list;
|
||||
@ -210,16 +218,16 @@ static void assign_requested_resources_sorted(struct resource_list *head,
|
||||
}
|
||||
|
||||
static void __assign_resources_sorted(struct resource_list *head,
|
||||
struct resource_list_x *add_head,
|
||||
struct resource_list_x *realloc_head,
|
||||
struct resource_list_x *fail_head)
|
||||
{
|
||||
/* Satisfy the must-have resource requests */
|
||||
assign_requested_resources_sorted(head, fail_head);
|
||||
|
||||
/* Try to satisfy any additional nice-to-have resource
|
||||
/* Try to satisfy any additional optional resource
|
||||
requests */
|
||||
if (add_head)
|
||||
adjust_resources_sorted(add_head, head);
|
||||
if (realloc_head)
|
||||
reassign_resources_sorted(realloc_head, head);
|
||||
free_list(resource_list, head);
|
||||
}
|
||||
|
||||
@ -235,7 +243,7 @@ static void pdev_assign_resources_sorted(struct pci_dev *dev,
|
||||
}
|
||||
|
||||
static void pbus_assign_resources_sorted(const struct pci_bus *bus,
|
||||
struct resource_list_x *add_head,
|
||||
struct resource_list_x *realloc_head,
|
||||
struct resource_list_x *fail_head)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
@ -245,7 +253,7 @@ static void pbus_assign_resources_sorted(const struct pci_bus *bus,
|
||||
list_for_each_entry(dev, &bus->devices, bus_list)
|
||||
__dev_sort_resources(dev, &head);
|
||||
|
||||
__assign_resources_sorted(&head, add_head, fail_head);
|
||||
__assign_resources_sorted(&head, realloc_head, fail_head);
|
||||
}
|
||||
|
||||
void pci_setup_cardbus(struct pci_bus *bus)
|
||||
@ -540,13 +548,27 @@ static resource_size_t calculate_memsize(resource_size_t size,
|
||||
return size;
|
||||
}
|
||||
|
||||
static resource_size_t get_res_add_size(struct resource_list_x *realloc_head,
|
||||
struct resource *res)
|
||||
{
|
||||
struct resource_list_x *list;
|
||||
|
||||
/* check if it is in realloc_head list */
|
||||
for (list = realloc_head->next; list && list->res != res;
|
||||
list = list->next);
|
||||
if (list)
|
||||
return list->add_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pbus_size_io() - size the io window of a given bus
|
||||
*
|
||||
* @bus : the bus
|
||||
* @min_size : the minimum io window that must to be allocated
|
||||
* @add_size : additional optional io window
|
||||
* @add_head : track the additional io window on this list
|
||||
* @realloc_head : track the additional io window on this list
|
||||
*
|
||||
* Sizing the IO windows of the PCI-PCI bridge is trivial,
|
||||
* since these windows have 4K granularity and the IO ranges
|
||||
@ -554,11 +576,12 @@ static resource_size_t calculate_memsize(resource_size_t size,
|
||||
* We must be careful with the ISA aliasing though.
|
||||
*/
|
||||
static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
||||
resource_size_t add_size, struct resource_list_x *add_head)
|
||||
resource_size_t add_size, struct resource_list_x *realloc_head)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
|
||||
unsigned long size = 0, size0 = 0, size1 = 0;
|
||||
resource_size_t children_add_size = 0;
|
||||
|
||||
if (!b_res)
|
||||
return;
|
||||
@ -579,11 +602,16 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
||||
size += r_size;
|
||||
else
|
||||
size1 += r_size;
|
||||
|
||||
if (realloc_head)
|
||||
children_add_size += get_res_add_size(realloc_head, r);
|
||||
}
|
||||
}
|
||||
size0 = calculate_iosize(size, min_size, size1,
|
||||
resource_size(b_res), 4096);
|
||||
size1 = (!add_head || (add_head && !add_size)) ? size0 :
|
||||
if (children_add_size > add_size)
|
||||
add_size = children_add_size;
|
||||
size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
|
||||
calculate_iosize(size, min_size+add_size, size1,
|
||||
resource_size(b_res), 4096);
|
||||
if (!size0 && !size1) {
|
||||
@ -598,8 +626,8 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
||||
b_res->start = 4096;
|
||||
b_res->end = b_res->start + size0 - 1;
|
||||
b_res->flags |= IORESOURCE_STARTALIGN;
|
||||
if (size1 > size0 && add_head)
|
||||
add_to_list(add_head, bus->self, b_res, size1-size0);
|
||||
if (size1 > size0 && realloc_head)
|
||||
add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -608,7 +636,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
||||
* @bus : the bus
|
||||
* @min_size : the minimum memory window that must to be allocated
|
||||
* @add_size : additional optional memory window
|
||||
* @add_head : track the additional memory window on this list
|
||||
* @realloc_head : track the additional memory window on this list
|
||||
*
|
||||
* Calculate the size of the bus and minimal alignment which
|
||||
* guarantees that all child resources fit in this size.
|
||||
@ -616,7 +644,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
||||
static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
unsigned long type, resource_size_t min_size,
|
||||
resource_size_t add_size,
|
||||
struct resource_list_x *add_head)
|
||||
struct resource_list_x *realloc_head)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
resource_size_t min_align, align, size, size0, size1;
|
||||
@ -624,6 +652,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
int order, max_order;
|
||||
struct resource *b_res = find_free_bus_resource(bus, type);
|
||||
unsigned int mem64_mask = 0;
|
||||
resource_size_t children_add_size = 0;
|
||||
|
||||
if (!b_res)
|
||||
return 0;
|
||||
@ -645,6 +674,16 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
if (r->parent || (r->flags & mask) != type)
|
||||
continue;
|
||||
r_size = resource_size(r);
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
/* put SRIOV requested res to the optional list */
|
||||
if (realloc_head && i >= PCI_IOV_RESOURCES &&
|
||||
i <= PCI_IOV_RESOURCE_END) {
|
||||
r->end = r->start - 1;
|
||||
add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
|
||||
children_add_size += r_size;
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
/* For bridges size != alignment */
|
||||
align = pci_resource_alignment(dev, r);
|
||||
order = __ffs(align) - 20;
|
||||
@ -665,6 +704,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
if (order > max_order)
|
||||
max_order = order;
|
||||
mem64_mask &= r->flags & IORESOURCE_MEM_64;
|
||||
|
||||
if (realloc_head)
|
||||
children_add_size += get_res_add_size(realloc_head, r);
|
||||
}
|
||||
}
|
||||
align = 0;
|
||||
@ -681,7 +723,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
align += aligns[order];
|
||||
}
|
||||
size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
|
||||
size1 = (!add_head || (add_head && !add_size)) ? size0 :
|
||||
if (children_add_size > add_size)
|
||||
add_size = children_add_size;
|
||||
size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
|
||||
calculate_memsize(size, min_size+add_size, 0,
|
||||
resource_size(b_res), min_align);
|
||||
if (!size0 && !size1) {
|
||||
@ -695,12 +739,22 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
b_res->start = min_align;
|
||||
b_res->end = size0 + min_align - 1;
|
||||
b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
|
||||
if (size1 > size0 && add_head)
|
||||
add_to_list(add_head, bus->self, b_res, size1-size0);
|
||||
if (size1 > size0 && realloc_head)
|
||||
add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void pci_bus_size_cardbus(struct pci_bus *bus)
|
||||
unsigned long pci_cardbus_resource_alignment(struct resource *res)
|
||||
{
|
||||
if (res->flags & IORESOURCE_IO)
|
||||
return pci_cardbus_io_size;
|
||||
if (res->flags & IORESOURCE_MEM)
|
||||
return pci_cardbus_mem_size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
struct resource_list_x *realloc_head)
|
||||
{
|
||||
struct pci_dev *bridge = bus->self;
|
||||
struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
|
||||
@ -711,12 +765,14 @@ static void pci_bus_size_cardbus(struct pci_bus *bus)
|
||||
* a fixed amount of bus space for CardBus bridges.
|
||||
*/
|
||||
b_res[0].start = 0;
|
||||
b_res[0].end = pci_cardbus_io_size - 1;
|
||||
b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
|
||||
if (realloc_head)
|
||||
add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */);
|
||||
|
||||
b_res[1].start = 0;
|
||||
b_res[1].end = pci_cardbus_io_size - 1;
|
||||
b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
|
||||
if (realloc_head)
|
||||
add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */);
|
||||
|
||||
/*
|
||||
* Check whether prefetchable memory is supported
|
||||
@ -736,21 +792,31 @@ static void pci_bus_size_cardbus(struct pci_bus *bus)
|
||||
*/
|
||||
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
|
||||
b_res[2].start = 0;
|
||||
b_res[2].end = pci_cardbus_mem_size - 1;
|
||||
b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
|
||||
if (realloc_head)
|
||||
add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */);
|
||||
|
||||
b_res[3].start = 0;
|
||||
b_res[3].end = pci_cardbus_mem_size - 1;
|
||||
b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
|
||||
if (realloc_head)
|
||||
add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */);
|
||||
} else {
|
||||
b_res[3].start = 0;
|
||||
b_res[3].end = pci_cardbus_mem_size * 2 - 1;
|
||||
b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
|
||||
if (realloc_head)
|
||||
add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */);
|
||||
}
|
||||
|
||||
/* set the size of the resource to zero, so that the resource does not
|
||||
* get assigned during required-resource allocation cycle but gets assigned
|
||||
* during the optional-resource allocation cycle.
|
||||
*/
|
||||
b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1;
|
||||
b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0;
|
||||
}
|
||||
|
||||
void __ref __pci_bus_size_bridges(struct pci_bus *bus,
|
||||
struct resource_list_x *add_head)
|
||||
struct resource_list_x *realloc_head)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
unsigned long mask, prefmask;
|
||||
@ -763,12 +829,12 @@ void __ref __pci_bus_size_bridges(struct pci_bus *bus,
|
||||
|
||||
switch (dev->class >> 8) {
|
||||
case PCI_CLASS_BRIDGE_CARDBUS:
|
||||
pci_bus_size_cardbus(b);
|
||||
pci_bus_size_cardbus(b, realloc_head);
|
||||
break;
|
||||
|
||||
case PCI_CLASS_BRIDGE_PCI:
|
||||
default:
|
||||
__pci_bus_size_bridges(b, add_head);
|
||||
__pci_bus_size_bridges(b, realloc_head);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -792,7 +858,7 @@ void __ref __pci_bus_size_bridges(struct pci_bus *bus,
|
||||
* Follow thru
|
||||
*/
|
||||
default:
|
||||
pbus_size_io(bus, 0, additional_io_size, add_head);
|
||||
pbus_size_io(bus, 0, additional_io_size, realloc_head);
|
||||
/* If the bridge supports prefetchable range, size it
|
||||
separately. If it doesn't, or its prefetchable window
|
||||
has already been allocated by arch code, try
|
||||
@ -800,11 +866,11 @@ void __ref __pci_bus_size_bridges(struct pci_bus *bus,
|
||||
resources. */
|
||||
mask = IORESOURCE_MEM;
|
||||
prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
||||
if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, add_head))
|
||||
if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, realloc_head))
|
||||
mask = prefmask; /* Success, size non-prefetch only. */
|
||||
else
|
||||
additional_mem_size += additional_mem_size;
|
||||
pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, add_head);
|
||||
pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, realloc_head);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -816,20 +882,20 @@ void __ref pci_bus_size_bridges(struct pci_bus *bus)
|
||||
EXPORT_SYMBOL(pci_bus_size_bridges);
|
||||
|
||||
static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
|
||||
struct resource_list_x *add_head,
|
||||
struct resource_list_x *realloc_head,
|
||||
struct resource_list_x *fail_head)
|
||||
{
|
||||
struct pci_bus *b;
|
||||
struct pci_dev *dev;
|
||||
|
||||
pbus_assign_resources_sorted(bus, add_head, fail_head);
|
||||
pbus_assign_resources_sorted(bus, realloc_head, fail_head);
|
||||
|
||||
list_for_each_entry(dev, &bus->devices, bus_list) {
|
||||
b = dev->subordinate;
|
||||
if (!b)
|
||||
continue;
|
||||
|
||||
__pci_bus_assign_resources(b, add_head, fail_head);
|
||||
__pci_bus_assign_resources(b, realloc_head, fail_head);
|
||||
|
||||
switch (dev->class >> 8) {
|
||||
case PCI_CLASS_BRIDGE_PCI:
|
||||
@ -1039,7 +1105,7 @@ void __init
|
||||
pci_assign_unassigned_resources(void)
|
||||
{
|
||||
struct pci_bus *bus;
|
||||
struct resource_list_x add_list; /* list of resources that
|
||||
struct resource_list_x realloc_list; /* list of resources that
|
||||
want additional resources */
|
||||
int tried_times = 0;
|
||||
enum release_type rel_type = leaf_only;
|
||||
@ -1052,7 +1118,7 @@ pci_assign_unassigned_resources(void)
|
||||
|
||||
|
||||
head.next = NULL;
|
||||
add_list.next = NULL;
|
||||
realloc_list.next = NULL;
|
||||
|
||||
pci_try_num = max_depth + 1;
|
||||
printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
|
||||
@ -1062,12 +1128,12 @@ again:
|
||||
/* Depth first, calculate sizes and alignments of all
|
||||
subordinate buses. */
|
||||
list_for_each_entry(bus, &pci_root_buses, node)
|
||||
__pci_bus_size_bridges(bus, &add_list);
|
||||
__pci_bus_size_bridges(bus, &realloc_list);
|
||||
|
||||
/* Depth last, allocate resources and update the hardware. */
|
||||
list_for_each_entry(bus, &pci_root_buses, node)
|
||||
__pci_bus_assign_resources(bus, &add_list, &head);
|
||||
BUG_ON(add_list.next);
|
||||
__pci_bus_assign_resources(bus, &realloc_list, &head);
|
||||
BUG_ON(realloc_list.next);
|
||||
tried_times++;
|
||||
|
||||
/* any device complain? */
|
||||
|
||||
@ -128,16 +128,16 @@ void pci_disable_bridge_window(struct pci_dev *dev)
|
||||
}
|
||||
#endif /* CONFIG_PCI_QUIRKS */
|
||||
|
||||
|
||||
|
||||
static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
|
||||
int resno)
|
||||
int resno, resource_size_t size, resource_size_t align)
|
||||
{
|
||||
struct resource *res = dev->resource + resno;
|
||||
resource_size_t size, min, align;
|
||||
resource_size_t min;
|
||||
int ret;
|
||||
|
||||
size = resource_size(res);
|
||||
min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
|
||||
align = pci_resource_alignment(dev, res);
|
||||
|
||||
/* First, try exact prefetching match.. */
|
||||
ret = pci_bus_alloc_resource(bus, res, size, align, min,
|
||||
@ -154,16 +154,15 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
|
||||
ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
|
||||
pcibios_align_resource, dev);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (ret < 0 && dev->fw_addr[resno]) {
|
||||
static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
|
||||
int resno, resource_size_t size)
|
||||
{
|
||||
struct resource *root, *conflict;
|
||||
resource_size_t start, end;
|
||||
|
||||
/*
|
||||
* If we failed to assign anything, let's try the address
|
||||
* where firmware left it. That at least has a chance of
|
||||
* working, which is better than just leaving it disabled.
|
||||
*/
|
||||
int ret = 0;
|
||||
|
||||
if (res->flags & IORESOURCE_IO)
|
||||
root = &ioport_resource;
|
||||
@ -183,44 +182,23 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
|
||||
res, conflict->name, conflict);
|
||||
res->start = start;
|
||||
res->end = end;
|
||||
} else
|
||||
ret = 0;
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
if (!ret) {
|
||||
res->flags &= ~IORESOURCE_STARTALIGN;
|
||||
dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
|
||||
if (resno < PCI_BRIDGE_RESOURCES)
|
||||
pci_update_resource(dev, resno);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int pci_assign_resource(struct pci_dev *dev, int resno)
|
||||
static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
|
||||
{
|
||||
struct resource *res = dev->resource + resno;
|
||||
resource_size_t align;
|
||||
struct pci_bus *bus;
|
||||
int ret;
|
||||
char *type;
|
||||
|
||||
align = pci_resource_alignment(dev, res);
|
||||
if (!align) {
|
||||
dev_info(&dev->dev, "BAR %d: can't assign %pR "
|
||||
"(bogus alignment)\n", resno, res);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bus = dev->bus;
|
||||
while ((ret = __pci_assign_resource(bus, dev, resno))) {
|
||||
if (bus->parent && bus->self->transparent)
|
||||
bus = bus->parent;
|
||||
else
|
||||
bus = NULL;
|
||||
if (bus)
|
||||
continue;
|
||||
while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
|
||||
if (!bus->parent || !bus->self->transparent)
|
||||
break;
|
||||
bus = bus->parent;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
@ -241,6 +219,66 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
|
||||
return ret;
|
||||
}
|
||||
|
||||
int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
|
||||
resource_size_t min_align)
|
||||
{
|
||||
struct resource *res = dev->resource + resno;
|
||||
resource_size_t new_size;
|
||||
int ret;
|
||||
|
||||
if (!res->parent) {
|
||||
dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
|
||||
"\n", resno, res);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
new_size = resource_size(res) + addsize + min_align;
|
||||
ret = _pci_assign_resource(dev, resno, new_size, min_align);
|
||||
if (!ret) {
|
||||
res->flags &= ~IORESOURCE_STARTALIGN;
|
||||
dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
|
||||
if (resno < PCI_BRIDGE_RESOURCES)
|
||||
pci_update_resource(dev, resno);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int pci_assign_resource(struct pci_dev *dev, int resno)
|
||||
{
|
||||
struct resource *res = dev->resource + resno;
|
||||
resource_size_t align, size;
|
||||
struct pci_bus *bus;
|
||||
int ret;
|
||||
|
||||
align = pci_resource_alignment(dev, res);
|
||||
if (!align) {
|
||||
dev_info(&dev->dev, "BAR %d: can't assign %pR "
|
||||
"(bogus alignment)\n", resno, res);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bus = dev->bus;
|
||||
size = resource_size(res);
|
||||
ret = _pci_assign_resource(dev, resno, size, align);
|
||||
|
||||
/*
|
||||
* If we failed to assign anything, let's try the address
|
||||
* where firmware left it. That at least has a chance of
|
||||
* working, which is better than just leaving it disabled.
|
||||
*/
|
||||
if (ret < 0 && dev->fw_addr[resno])
|
||||
ret = pci_revert_fw_address(res, dev, resno, size);
|
||||
|
||||
if (!ret) {
|
||||
res->flags &= ~IORESOURCE_STARTALIGN;
|
||||
dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
|
||||
if (resno < PCI_BRIDGE_RESOURCES)
|
||||
pci_update_resource(dev, resno);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/* Sort resources by alignment */
|
||||
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
|
||||
{
|
||||
|
||||
@ -251,7 +251,8 @@ struct pci_dev {
|
||||
u8 revision; /* PCI revision, low byte of class word */
|
||||
u8 hdr_type; /* PCI header type (`multi' flag masked out) */
|
||||
u8 pcie_cap; /* PCI-E capability offset */
|
||||
u8 pcie_type; /* PCI-E device/port type */
|
||||
u8 pcie_type:4; /* PCI-E device/port type */
|
||||
u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
|
||||
u8 rom_base_reg; /* which config register controls the ROM */
|
||||
u8 pin; /* which interrupt pin this device uses */
|
||||
|
||||
@ -617,6 +618,16 @@ struct pci_driver {
|
||||
/* these external functions are only available when PCI support is enabled */
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
|
||||
|
||||
enum pcie_bus_config_types {
|
||||
PCIE_BUS_PERFORMANCE,
|
||||
PCIE_BUS_SAFE,
|
||||
PCIE_BUS_PEER2PEER,
|
||||
};
|
||||
|
||||
extern enum pcie_bus_config_types pcie_bus_config;
|
||||
|
||||
extern struct bus_type pci_bus_type;
|
||||
|
||||
/* Do NOT directly access these two variables, unless you are arch specific pci
|
||||
@ -796,10 +807,13 @@ int pcix_get_mmrbc(struct pci_dev *dev);
|
||||
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
|
||||
int pcie_get_readrq(struct pci_dev *dev);
|
||||
int pcie_set_readrq(struct pci_dev *dev, int rq);
|
||||
int pcie_get_mps(struct pci_dev *dev);
|
||||
int pcie_set_mps(struct pci_dev *dev, int mps);
|
||||
int __pci_reset_function(struct pci_dev *dev);
|
||||
int pci_reset_function(struct pci_dev *dev);
|
||||
void pci_update_resource(struct pci_dev *dev, int resno);
|
||||
int __must_check pci_assign_resource(struct pci_dev *dev, int i);
|
||||
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
|
||||
int pci_select_bars(struct pci_dev *dev, unsigned long flags);
|
||||
|
||||
/* ROM control related routines */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user