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Merge branch 'cxgb4-collect-LE-TCAM-and-SGE-queue-contexts'

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Rahul Lakkireddy says:

====================
cxgb4: collect LE-TCAM and SGE queue contexts

Collect hardware dumps via ethtool --get-dump facility.

Patch 1 collects LE-TCAM dump.

Patch 2 collects SGE queue context dumps.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2017-11-14 16:14:07 +09:00
commit 0c3ce16cb7
9 changed files with 456 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
View File

@ -145,6 +145,14 @@ struct cudbg_tid_info_region_rev1 {
u32 reserved[16];
};
#define CUDBG_MAX_FL_QIDS 1024
struct cudbg_ch_cntxt {
u32 cntxt_type;
u32 cntxt_id;
u32 data[SGE_CTXT_SIZE / 4];
};
#define CUDBG_MAX_RPLC_SIZE 128
struct cudbg_mps_tcam {
@ -185,6 +193,36 @@ struct cudbg_vpd_data {
u32 vpd_vers;
};
#define CUDBG_MAX_TCAM_TID 0x800
enum cudbg_le_entry_types {
LE_ET_UNKNOWN = 0,
LE_ET_TCAM_CON = 1,
LE_ET_TCAM_SERVER = 2,
LE_ET_TCAM_FILTER = 3,
LE_ET_TCAM_CLIP = 4,
LE_ET_TCAM_ROUTING = 5,
LE_ET_HASH_CON = 6,
LE_ET_INVALID_TID = 8,
};
struct cudbg_tcam {
u32 filter_start;
u32 server_start;
u32 clip_start;
u32 routing_start;
u32 tid_hash_base;
u32 max_tid;
};
struct cudbg_tid_data {
u32 tid;
u32 dbig_cmd;
u32 dbig_conf;
u32 dbig_rsp_stat;
u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
};
#define CUDBG_NUM_ULPTX 11
#define CUDBG_NUM_ULPTX_READ 512

2
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
View File

@ -63,8 +63,10 @@ enum cudbg_dbg_entity_type {
CUDBG_PCIE_INDIRECT = 50,
CUDBG_PM_INDIRECT = 51,
CUDBG_TID_INFO = 54,
CUDBG_DUMP_CONTEXT = 56,
CUDBG_MPS_TCAM = 57,
CUDBG_VPD_DATA = 58,
CUDBG_LE_TCAM = 59,
CUDBG_CCTRL = 60,
CUDBG_MA_INDIRECT = 61,
CUDBG_ULPTX_LA = 62,

253
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
View File

@ -1115,6 +1115,84 @@ int cudbg_collect_tid(struct cudbg_init *pdbg_init,
return rc;
}
int cudbg_dump_context_size(struct adapter *padap)
{
u32 value, size;
u8 flq;
value = t4_read_reg(padap, SGE_FLM_CFG_A);
/* Get number of data freelist queues */
flq = HDRSTARTFLQ_G(value);
size = CUDBG_MAX_FL_QIDS >> flq;
/* Add extra space for congestion manager contexts.
* The number of CONM contexts are same as number of freelist
* queues.
*/
size += size;
return size * sizeof(struct cudbg_ch_cntxt);
}
static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
enum ctxt_type ctype, u32 *data)
{
struct adapter *padap = pdbg_init->adap;
int rc = -1;
/* Under heavy traffic, the SGE Queue contexts registers will be
* frequently accessed by firmware.
*
* To avoid conflicts with firmware, always ask firmware to fetch
* the SGE Queue contexts via mailbox. On failure, fallback to
* accessing hardware registers directly.
*/
if (is_fw_attached(pdbg_init))
rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data);
if (rc)
t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
}
int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
struct cudbg_ch_cntxt *buff;
u32 size, i = 0;
int rc;
rc = cudbg_dump_context_size(padap);
if (rc <= 0)
return CUDBG_STATUS_ENTITY_NOT_FOUND;
size = rc;
rc = cudbg_get_buff(dbg_buff, size, &temp_buff);
if (rc)
return rc;
buff = (struct cudbg_ch_cntxt *)temp_buff.data;
while (size > 0) {
buff->cntxt_type = CTXT_FLM;
buff->cntxt_id = i;
cudbg_read_sge_ctxt(pdbg_init, i, CTXT_FLM, buff->data);
buff++;
size -= sizeof(struct cudbg_ch_cntxt);
buff->cntxt_type = CTXT_CNM;
buff->cntxt_id = i;
cudbg_read_sge_ctxt(pdbg_init, i, CTXT_CNM, buff->data);
buff++;
size -= sizeof(struct cudbg_ch_cntxt);
i++;
}
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
return rc;
}
static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
{
*mask = x | y;
@ -1367,6 +1445,181 @@ int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
return rc;
}
static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid,
struct cudbg_tid_data *tid_data)
{
struct adapter *padap = pdbg_init->adap;
int i, cmd_retry = 8;
u32 val;
/* Fill REQ_DATA regs with 0's */
for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++)
t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
/* Write DBIG command */
val = DBGICMD_V(4) | DBGITID_V(tid);
t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
tid_data->dbig_cmd = val;
val = DBGICMDSTRT_F | DBGICMDMODE_V(1); /* LE mode */
t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
tid_data->dbig_conf = val;
/* Poll the DBGICMDBUSY bit */
val = 1;
while (val) {
val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A);
val = val & DBGICMDBUSY_F;
cmd_retry--;
if (!cmd_retry)
return CUDBG_SYSTEM_ERROR;
}
/* Check RESP status */
val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A);
tid_data->dbig_rsp_stat = val;
if (!(val & 1))
return CUDBG_SYSTEM_ERROR;
/* Read RESP data */
for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++)
tid_data->data[i] = t4_read_reg(padap,
LE_DB_DBGI_RSP_DATA_A +
(i << 2));
tid_data->tid = tid;
return 0;
}
static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region)
{
int type = LE_ET_UNKNOWN;
if (tid < tcam_region.server_start)
type = LE_ET_TCAM_CON;
else if (tid < tcam_region.filter_start)
type = LE_ET_TCAM_SERVER;
else if (tid < tcam_region.clip_start)
type = LE_ET_TCAM_FILTER;
else if (tid < tcam_region.routing_start)
type = LE_ET_TCAM_CLIP;
else if (tid < tcam_region.tid_hash_base)
type = LE_ET_TCAM_ROUTING;
else if (tid < tcam_region.max_tid)
type = LE_ET_HASH_CON;
else
type = LE_ET_INVALID_TID;
return type;
}
static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data,
struct cudbg_tcam tcam_region)
{
int ipv6 = 0;
int le_type;
le_type = cudbg_get_le_type(tid_data->tid, tcam_region);
if (tid_data->tid & 1)
return 0;
if (le_type == LE_ET_HASH_CON) {
ipv6 = tid_data->data[16] & 0x8000;
} else if (le_type == LE_ET_TCAM_CON) {
ipv6 = tid_data->data[16] & 0x8000;
if (ipv6)
ipv6 = tid_data->data[9] == 0x00C00000;
} else {
ipv6 = 0;
}
return ipv6;
}
void cudbg_fill_le_tcam_info(struct adapter *padap,
struct cudbg_tcam *tcam_region)
{
u32 value;
/* Get the LE regions */
value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A); /* hash base index */
tcam_region->tid_hash_base = value;
/* Get routing table index */
value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A);
tcam_region->routing_start = value;
/*Get clip table index */
value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A);
tcam_region->clip_start = value;
/* Get filter table index */
value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A);
tcam_region->filter_start = value;
/* Get server table index */
value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A);
tcam_region->server_start = value;
/* Check whether hash is enabled and calculate the max tids */
value = t4_read_reg(padap, LE_DB_CONFIG_A);
if ((value >> HASHEN_S) & 1) {
value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A);
if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
tcam_region->max_tid = (value & 0xFFFFF) +
tcam_region->tid_hash_base;
} else {
value = HASHTIDSIZE_G(value);
value = 1 << value;
tcam_region->max_tid = value +
tcam_region->tid_hash_base;
}
} else { /* hash not enabled */
tcam_region->max_tid = CUDBG_MAX_TCAM_TID;
}
}
int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_buffer temp_buff = { 0 };
struct cudbg_tcam tcam_region = { 0 };
struct cudbg_tid_data *tid_data;
u32 bytes = 0;
int rc, size;
u32 i;
cudbg_fill_le_tcam_info(padap, &tcam_region);
size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
size += sizeof(struct cudbg_tcam);
rc = cudbg_get_buff(dbg_buff, size, &temp_buff);
if (rc)
return rc;
memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam));
bytes = sizeof(struct cudbg_tcam);
tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes);
/* read all tid */
for (i = 0; i < tcam_region.max_tid; ) {
rc = cudbg_read_tid(pdbg_init, i, tid_data);
if (rc) {
cudbg_err->sys_err = rc;
cudbg_put_buff(&temp_buff, dbg_buff);
return rc;
}
/* ipv6 takes two tids */
cudbg_is_ipv6_entry(tid_data, tcam_region) ? i += 2 : i++;
tid_data++;
bytes += sizeof(struct cudbg_tid_data);
}
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
return rc;
}
int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)

11
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
View File

@ -123,12 +123,18 @@ int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
int cudbg_collect_tid(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
@ -155,4 +161,9 @@ struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i);
void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
struct cudbg_entity_hdr *entity_hdr);
u32 cudbg_cim_obq_size(struct adapter *padap, int qid);
int cudbg_dump_context_size(struct adapter *padap);
struct cudbg_tcam;
void cudbg_fill_le_tcam_info(struct adapter *padap,
struct cudbg_tcam *tcam_region);
#endif /* __CUDBG_LIB_H__ */

4
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
View File

@ -1670,6 +1670,10 @@ int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
enum ctxt_type ctype, u32 *data);
int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
enum ctxt_type ctype, u32 *data);
int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
int rateunit, int ratemode, int channel, int class,
int minrate, int maxrate, int weight, int pktsize);

11
drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
View File

@ -60,8 +60,10 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },
{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },
{ CUDBG_TID_INFO, cudbg_collect_tid },
{ CUDBG_DUMP_CONTEXT, cudbg_collect_dump_context },
{ CUDBG_MPS_TCAM, cudbg_collect_mps_tcam },
{ CUDBG_VPD_DATA, cudbg_collect_vpd_data },
{ CUDBG_LE_TCAM, cudbg_collect_le_tcam },
{ CUDBG_CCTRL, cudbg_collect_cctrl },
{ CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect },
{ CUDBG_ULPTX_LA, cudbg_collect_ulptx_la },
@ -72,6 +74,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
{
struct cudbg_tcam tcam_region = { 0 };
u32 value, n = 0, len = 0;
switch (entity) {
@ -216,6 +219,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
case CUDBG_TID_INFO:
len = sizeof(struct cudbg_tid_info_region_rev1);
break;
case CUDBG_DUMP_CONTEXT:
len = cudbg_dump_context_size(adap);
break;
case CUDBG_MPS_TCAM:
len = sizeof(struct cudbg_mps_tcam) *
adap->params.arch.mps_tcam_size;
@ -223,6 +229,11 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
case CUDBG_VPD_DATA:
len = sizeof(struct cudbg_vpd_data);
break;
case CUDBG_LE_TCAM:
cudbg_fill_le_tcam_info(adap, &tcam_region);
len = sizeof(struct cudbg_tcam) +
sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
break;
case CUDBG_CCTRL:
len = sizeof(u16) * NMTUS * NCCTRL_WIN;
break;

62
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View File

@ -9647,6 +9647,68 @@ void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
}
}
/* t4_sge_ctxt_rd - read an SGE context through FW
* @adap: the adapter
* @mbox: mailbox to use for the FW command
* @cid: the context id
* @ctype: the context type
* @data: where to store the context data
*
* Issues a FW command through the given mailbox to read an SGE context.
*/
int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
enum ctxt_type ctype, u32 *data)
{
struct fw_ldst_cmd c;
int ret;
if (ctype == CTXT_FLM)
ret = FW_LDST_ADDRSPC_SGE_FLMC;
else
ret = FW_LDST_ADDRSPC_SGE_CONMC;
memset(&c, 0, sizeof(c));
c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F |
FW_LDST_CMD_ADDRSPACE_V(ret));
c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
c.u.idctxt.physid = cpu_to_be32(cid);
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
if (ret == 0) {
data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
}
return ret;
}
/**
* t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
* @adap: the adapter
* @cid: the context id
* @ctype: the context type
* @data: where to store the context data
*
* Reads an SGE context directly, bypassing FW. This is only for
* debugging when FW is unavailable.
*/
int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
enum ctxt_type ctype, u32 *data)
{
int i, ret;
t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
if (!ret)
for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
*data++ = t4_read_reg(adap, i);
return ret;
}
int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
int rateunit, int ratemode, int channel, int class,
int minrate, int maxrate, int weight, int pktsize)

7
drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
View File

@ -68,6 +68,12 @@ enum {
ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
};
/* SGE context types */
enum ctxt_type {
CTXT_FLM = 2,
CTXT_CNM,
};
enum {
SF_PAGE_SIZE = 256, /* serial flash page size */
SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
@ -79,6 +85,7 @@ enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
enum {
SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
SGE_CTXT_SIZE = 24, /* size of SGE context */
SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
SGE_MAX_IQ_SIZE = 65520,

68
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View File

@ -65,6 +65,9 @@
#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
#define SGE_PF_KDOORBELL_A 0x0
#define QID_S 15
@ -150,6 +153,23 @@
#define T6_DBVFIFO_SIZE_M 0x1fffU
#define T6_DBVFIFO_SIZE_G(x) (((x) >> T6_DBVFIFO_SIZE_S) & T6_DBVFIFO_SIZE_M)
#define SGE_CTXT_CMD_A 0x11fc
#define BUSY_S 31
#define BUSY_V(x) ((x) << BUSY_S)
#define BUSY_F BUSY_V(1U)
#define CTXTTYPE_S 24
#define CTXTTYPE_M 0x3U
#define CTXTTYPE_V(x) ((x) << CTXTTYPE_S)
#define CTXTQID_S 0
#define CTXTQID_M 0x1ffffU
#define CTXTQID_V(x) ((x) << CTXTQID_S)
#define SGE_CTXT_DATA0_A 0x1200
#define SGE_CTXT_DATA5_A 0x1214
#define GLOBALENABLE_S 0
#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
#define GLOBALENABLE_F GLOBALENABLE_V(1U)
@ -319,6 +339,16 @@
#define SGE_IMSG_CTXT_BADDR_A 0x1088
#define SGE_FLM_CACHE_BADDR_A 0x108c
#define SGE_FLM_CFG_A 0x1090
#define NOHDR_S 18
#define NOHDR_V(x) ((x) << NOHDR_S)
#define NOHDR_F NOHDR_V(1U)
#define HDRSTARTFLQ_S 11
#define HDRSTARTFLQ_M 0x7U
#define HDRSTARTFLQ_G(x) (((x) >> HDRSTARTFLQ_S) & HDRSTARTFLQ_M)
#define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
#define THRESHOLD_0_S 24
@ -2273,6 +2303,35 @@
#define CHNENABLE_V(x) ((x) << CHNENABLE_S)
#define CHNENABLE_F CHNENABLE_V(1U)
#define LE_DB_DBGI_CONFIG_A 0x19cf0
#define DBGICMDBUSY_S 3
#define DBGICMDBUSY_V(x) ((x) << DBGICMDBUSY_S)
#define DBGICMDBUSY_F DBGICMDBUSY_V(1U)
#define DBGICMDSTRT_S 2
#define DBGICMDSTRT_V(x) ((x) << DBGICMDSTRT_S)
#define DBGICMDSTRT_F DBGICMDSTRT_V(1U)
#define DBGICMDMODE_S 0
#define DBGICMDMODE_M 0x3U
#define DBGICMDMODE_V(x) ((x) << DBGICMDMODE_S)
#define LE_DB_DBGI_REQ_TCAM_CMD_A 0x19cf4
#define DBGICMD_S 20
#define DBGICMD_M 0xfU
#define DBGICMD_V(x) ((x) << DBGICMD_S)
#define DBGITID_S 0
#define DBGITID_M 0xfffffU
#define DBGITID_V(x) ((x) << DBGITID_S)
#define LE_DB_DBGI_REQ_DATA_A 0x19d00
#define LE_DB_DBGI_RSP_STATUS_A 0x19d94
#define LE_DB_DBGI_RSP_DATA_A 0x19da0
#define PRTENABLE_S 29
#define PRTENABLE_V(x) ((x) << PRTENABLE_S)
#define PRTENABLE_F PRTENABLE_V(1U)
@ -2882,11 +2941,20 @@
#define T6_LIPMISS_F T6_LIPMISS_V(1U)
#define LE_DB_CONFIG_A 0x19c04
#define LE_DB_ROUTING_TABLE_INDEX_A 0x19c10
#define LE_DB_ACTIVE_TABLE_START_INDEX_A 0x19c10
#define LE_DB_FILTER_TABLE_INDEX_A 0x19c14
#define LE_DB_SERVER_INDEX_A 0x19c18
#define LE_DB_SRVR_START_INDEX_A 0x19c18
#define LE_DB_CLIP_TABLE_INDEX_A 0x19c1c
#define LE_DB_ACT_CNT_IPV4_A 0x19c20
#define LE_DB_ACT_CNT_IPV6_A 0x19c24
#define LE_DB_HASH_CONFIG_A 0x19c28
#define HASHTIDSIZE_S 16
#define HASHTIDSIZE_M 0x3fU
#define HASHTIDSIZE_G(x) (((x) >> HASHTIDSIZE_S) & HASHTIDSIZE_M)
#define LE_DB_HASH_TID_BASE_A 0x19c30
#define LE_DB_HASH_TBL_BASE_ADDR_A 0x19c30
#define LE_DB_INT_CAUSE_A 0x19c3c