drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines
Follow consistent naming convention. Replace JSL with JASPERLAKE. Unroll IS_JSL_EHL() define with IS_JASPERLAKE() || IS_ELKHARTLAKE() condition. Change in the display step define for Jasperlake. v2: - Change subject prefix skl instead of SKL(Anusha) v3: - Remove the use of define IS_JSL_EHL. - Replace with IS_JASPERLAKE() || IS_ELKHARTLAKE() - Unrolled wrapper IS_JSL_ELK_DISPLAY_STEP (Jani/Tvrtko) v4: - Removed unused macro v5: - Resolved valid checkpatch warning(Jani) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-9-dnyaneshwar.bhadane@intel.com
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e549097972
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@ -444,7 +444,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
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intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
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/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
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if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
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if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
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(DISPLAY_VER(dev_priv) >= 12)) {
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intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
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LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
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@ -553,7 +554,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
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}
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}
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if (IS_JSL_EHL(dev_priv)) {
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if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
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for_each_dsi_phy(phy, intel_dsi->phys)
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intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
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0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
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@ -3155,7 +3155,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
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*/
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void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
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{
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if (IS_JSL_EHL(dev_priv)) {
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if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
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if (dev_priv->display.cdclk.hw.ref == 24000)
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dev_priv->display.cdclk.max_cdclk_freq = 552000;
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else
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@ -3583,7 +3583,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
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} else if (DISPLAY_VER(dev_priv) >= 12) {
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dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
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dev_priv->display.cdclk.table = icl_cdclk_table;
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} else if (IS_JSL_EHL(dev_priv)) {
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} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
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dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
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dev_priv->display.cdclk.table = icl_cdclk_table;
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} else if (DISPLAY_VER(dev_priv) >= 11) {
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@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
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if (IS_ALDERLAKE_S(i915))
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return phy == PHY_A;
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else if (IS_JSL_EHL(i915) ||
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else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||
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IS_ROCKETLAKE(i915) ||
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IS_DG1(i915))
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return phy < PHY_C;
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@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
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IREFGEN, IREFGEN);
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if (IS_JSL_EHL(dev_priv)) {
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if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
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if (ehl_vbt_ddi_d_present(dev_priv))
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expected_val = ICL_PHY_MISC_MUX_DDID;
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@ -333,7 +333,8 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
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* "internal" child devices.
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*/
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val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
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if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
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if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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phy == PHY_A) {
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val &= ~ICL_PHY_MISC_MUX_DDID;
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if (ehl_vbt_ddi_d_present(dev_priv))
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@ -3583,7 +3583,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
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{
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if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
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crtc_state->min_voltage_level = 2;
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else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
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else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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crtc_state->port_clock > 594000)
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crtc_state->min_voltage_level = 3;
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else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
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crtc_state->min_voltage_level = 1;
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@ -4878,7 +4879,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
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encoder->disable_clock = dg1_ddi_disable_clock;
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encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
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encoder->get_config = dg1_ddi_get_config;
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} else if (IS_JSL_EHL(dev_priv)) {
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} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
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if (intel_ddi_is_tc(dev_priv, port)) {
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encoder->enable_clock = jsl_ddi_tc_enable_clock;
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encoder->disable_clock = jsl_ddi_tc_disable_clock;
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@ -4949,7 +4950,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
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encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
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else if (DISPLAY_VER(dev_priv) >= 12)
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encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
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else if (IS_JSL_EHL(dev_priv))
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else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
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encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
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else if (DISPLAY_VER(dev_priv) == 11)
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encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
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@ -1749,7 +1749,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
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return phy <= PHY_E;
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else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
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return phy <= PHY_D;
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else if (IS_JSL_EHL(dev_priv))
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else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
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return phy <= PHY_C;
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else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
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return phy <= PHY_B;
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@ -1801,7 +1801,8 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
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return PHY_B + port - PORT_TC1;
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else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
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return PHY_C + port - PORT_TC1;
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else if (IS_JSL_EHL(i915) && port == PORT_D)
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else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
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port == PORT_D)
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return PHY_A;
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return PHY_A + port - PORT_A;
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@ -500,7 +500,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
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else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
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IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
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max_rate = 810000;
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else if (IS_JSL_EHL(dev_priv))
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else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
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max_rate = ehl_max_source_rate(intel_dp);
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else
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max_rate = icl_max_source_rate(intel_dp);
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@ -191,7 +191,8 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
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{
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if (IS_DG1(i915))
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return DG1_DPLL_ENABLE(pll->info->id);
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else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
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else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
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(pll->info->id == DPLL_ID_EHL_DPLL4))
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return MG_PLL_ENABLE(0);
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return ICL_DPLL_ENABLE(pll->info->id);
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@ -2460,8 +2461,8 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
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static bool
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ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
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{
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return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
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IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
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return (((IS_ELKHARTLAKE(i915) || IS_JASPERLAKE(i915)) &&
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IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
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IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
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i915->display.dpll.ref_clks.nssc == 38400;
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}
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@ -3226,7 +3227,8 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
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BIT(DPLL_ID_EHL_DPLL4) |
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BIT(DPLL_ID_ICL_DPLL1) |
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BIT(DPLL_ID_ICL_DPLL0);
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} else if (IS_JSL_EHL(dev_priv) && port != PORT_A) {
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} else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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port != PORT_A) {
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dpll_mask =
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BIT(DPLL_ID_EHL_DPLL4) |
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BIT(DPLL_ID_ICL_DPLL1) |
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@ -3567,7 +3569,8 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
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hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
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}
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} else {
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if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
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if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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id == DPLL_ID_EHL_DPLL4) {
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hw_state->cfgcr0 = intel_de_read(dev_priv,
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ICL_DPLL_CFGCR0(4));
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hw_state->cfgcr1 = intel_de_read(dev_priv,
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@ -3623,7 +3626,8 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
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cfgcr1_reg = TGL_DPLL_CFGCR1(id);
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div0_reg = TGL_DPLL0_DIV0(id);
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} else {
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if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
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if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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id == DPLL_ID_EHL_DPLL4) {
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cfgcr0_reg = ICL_DPLL_CFGCR0(4);
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cfgcr1_reg = ICL_DPLL_CFGCR1(4);
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} else {
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@ -3806,7 +3810,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
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{
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i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
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if (IS_JSL_EHL(dev_priv) &&
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if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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pll->info->id == DPLL_ID_EHL_DPLL4) {
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/*
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@ -3914,7 +3918,7 @@ static void combo_pll_disable(struct drm_i915_private *dev_priv,
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icl_pll_disable(dev_priv, pll, enable_reg);
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if (IS_JSL_EHL(dev_priv) &&
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if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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pll->info->id == DPLL_ID_EHL_DPLL4)
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intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,
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pll->wakeref);
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@ -4150,7 +4154,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
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dpll_mgr = &rkl_pll_mgr;
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else if (DISPLAY_VER(dev_priv) >= 12)
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dpll_mgr = &tgl_pll_mgr;
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else if (IS_JSL_EHL(dev_priv))
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else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
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dpll_mgr = &ehl_pll_mgr;
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else if (DISPLAY_VER(dev_priv) >= 11)
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dpll_mgr = &icl_pll_mgr;
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@ -4335,7 +4339,8 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
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pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
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if (IS_JSL_EHL(i915) && pll->on &&
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if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
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pll->on &&
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pll->info->id == DPLL_ID_EHL_DPLL4) {
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pll->wakeref = intel_display_power_get(i915,
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POWER_DOMAIN_DC_OFF);
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@ -2894,7 +2894,8 @@ static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder)
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ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
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else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
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ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
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else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
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else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
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HAS_PCH_TGP(dev_priv))
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ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
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else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
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ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
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@ -1074,7 +1074,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
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return false;
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/* JSL and EHL only supports eDP 1.3 */
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if (IS_JSL_EHL(dev_priv)) {
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if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
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drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
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return false;
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}
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@ -226,7 +226,7 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
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* it, but since i915 takes the stance of always zeroing memory before
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* handing it to userspace, we need to prevent this.
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*/
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return IS_JSL_EHL(i915);
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return (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915));
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}
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static void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
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@ -302,7 +302,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
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u8 eu_en;
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u8 s_en;
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if (IS_JSL_EHL(gt->i915))
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if (IS_JASPERLAKE(gt->i915) || IS_ELKHARTLAKE(gt->i915))
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intel_sseu_set_info(sseu, 1, 4, 8);
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else
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intel_sseu_set_info(sseu, 1, 8, 8);
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@ -1460,7 +1460,8 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
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/* Wa_1607087056:icl,ehl,jsl */
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if (IS_ICELAKE(i915) ||
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IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
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((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
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IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)))
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wa_write_or(wal,
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GEN11_SLICE_UNIT_LEVEL_CLKGATE,
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L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
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@ -561,8 +561,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
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#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
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#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
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#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
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IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
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#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
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#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
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#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
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#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
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#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
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@ -650,10 +650,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
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(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
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#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
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(IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
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#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
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(IS_TIGERLAKE(__i915) && \
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@ -219,7 +219,7 @@ void intel_step_init(struct drm_i915_private *i915)
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} else if (IS_TIGERLAKE(i915)) {
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revids = tgl_revids;
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size = ARRAY_SIZE(tgl_revids);
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} else if (IS_JSL_EHL(i915)) {
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} else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {
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revids = jsl_ehl_revids;
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size = ARRAY_SIZE(jsl_ehl_revids);
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} else if (IS_ICELAKE(i915)) {
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||||
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@ -115,7 +115,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
|
||||
return PCH_ICP;
|
||||
case INTEL_PCH_MCC_DEVICE_ID_TYPE:
|
||||
drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
|
||||
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
|
||||
drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) ||
|
||||
IS_ELKHARTLAKE(dev_priv)));
|
||||
/* MCC is TGP compatible */
|
||||
return PCH_TGP;
|
||||
case INTEL_PCH_TGP_DEVICE_ID_TYPE:
|
||||
@ -127,7 +128,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
|
||||
return PCH_TGP;
|
||||
case INTEL_PCH_JSP_DEVICE_ID_TYPE:
|
||||
drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
|
||||
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
|
||||
drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) ||
|
||||
IS_ELKHARTLAKE(dev_priv)));
|
||||
/* JSP is ICP compatible */
|
||||
return PCH_ICP;
|
||||
case INTEL_PCH_ADP_DEVICE_ID_TYPE:
|
||||
@ -177,7 +179,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
|
||||
id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
|
||||
else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
|
||||
id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
|
||||
else if (IS_JSL_EHL(dev_priv))
|
||||
else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
|
||||
id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
|
||||
else if (IS_ICELAKE(dev_priv))
|
||||
id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
|
||||
|
Loading…
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Reference in New Issue
Block a user