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Merge branch 'pci/misc'

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- Convert PCIe capability PCIBIOS errors to errno (Bolarinwa Olayemi
  Saheed)

- Align PCIe capability and PCI accessor return values (Bolarinwa Olayemi
  Saheed)

- Replace http:// links with https:// (Alexander A. Klimov)

- Replace lkml.org, spinics, gmane with lore.kernel.org (Bjorn Helgaas)

- Update panic message to mention kzalloc(), not kmalloc() (Liao Pingfang)

- Move PCI_VENDOR_ID_REDHAT definition to pci_ids.h (Huacai Chen)

- Remove unused pci_lost_interrupt() (Heiner Kallweit)

* pci/misc:
  PCI: Remove unused pci_lost_interrupt()
  PCI: Move PCI_VENDOR_ID_REDHAT definition to pci_ids.h
  PCI: Fix error in panic message
  PCI: Replace lkml.org, spinics, gmane with lore.kernel.org
  PCI: Replace http:// links with https://
  PCI: Align PCIe capability and PCI accessor return values
  PCI: Convert PCIe capability PCIBIOS errors to errno
This commit is contained in:
Bjorn Helgaas 2020-08-05 18:24:16 -05:00
commit 0caa17f5f2
28 changed files with 61 additions and 104 deletions
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9
Documentation/PCI/pci.rst
View File

@ -17,7 +17,7 @@ PCI device drivers.
A more complete resource is the third edition of "Linux Device Drivers" A more complete resource is the third edition of "Linux Device Drivers"
by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman. by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
LDD3 is available for free (under Creative Commons License) from: LDD3 is available for free (under Creative Commons License) from:
http://lwn.net/Kernel/LDD3/. https://lwn.net/Kernel/LDD3/.
However, keep in mind that all documents are subject to "bit rot". However, keep in mind that all documents are subject to "bit rot".
Refer to the source code if things are not working as described here. Refer to the source code if things are not working as described here.
@ -214,7 +214,7 @@ the PCI device by calling pci_enable_device(). This will:
problem and unlikely to get fixed soon. problem and unlikely to get fixed soon.
This has been discussed before but not changed as of 2.6.19: This has been discussed before but not changed as of 2.6.19:
http://lkml.org/lkml/2006/3/2/194 https://lore.kernel.org/r/20060302180025.GC28895@flint.arm.linux.org.uk/
pci_set_master() will enable DMA by setting the bus master bit pci_set_master() will enable DMA by setting the bus master bit
@ -514,9 +514,8 @@ your driver if they're helpful, or just use plain hex constants.
The device IDs are arbitrary hex numbers (vendor controlled) and normally used The device IDs are arbitrary hex numbers (vendor controlled) and normally used
only in a single location, the pci_device_id table. only in a single location, the pci_device_id table.
Please DO submit new vendor/device IDs to http://pci-ids.ucw.cz/. Please DO submit new vendor/device IDs to https://pci-ids.ucw.cz/.
There are mirrors of the pci.ids file at http://pciids.sourceforge.net/ There's a mirror of the pci.ids file at https://github.com/pciutils/pciids.
and https://github.com/pciutils/pciids.
Obsolete functions Obsolete functions

4
Documentation/devicetree/bindings/pci/pci.txt
View File

@ -1,12 +1,12 @@
PCI bus bridges have standardized Device Tree bindings: PCI bus bridges have standardized Device Tree bindings:
PCI Bus Binding to: IEEE Std 1275-1994 PCI Bus Binding to: IEEE Std 1275-1994
http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
And for the interrupt mapping part: And for the interrupt mapping part:
Open Firmware Recommended Practice: Interrupt Mapping Open Firmware Recommended Practice: Interrupt Mapping
http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
Additionally to the properties specified in the above standards a host bridge Additionally to the properties specified in the above standards a host bridge
driver implementation may support the following properties: driver implementation may support the following properties:

4
arch/x86/pci/fixup.c
View File

@ -557,12 +557,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_z
* Device [8086:2fc0] * Device [8086:2fc0]
* Erratum HSE43 * Erratum HSE43
* CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
* *
* Devices [8086:6f60,6fa0,6fc0] * Devices [8086:6f60,6fa0,6fc0]
* Erratum BDF2 * Erratum BDF2
* PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
*/ */
static void pci_invalid_bar(struct pci_dev *dev) static void pci_invalid_bar(struct pci_dev *dev)
{ {

4
drivers/dma/ioat/init.c
View File

@ -1195,13 +1195,13 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
/* disable relaxed ordering */ /* disable relaxed ordering */
err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16); err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
if (err) if (err)
return err; return pcibios_err_to_errno(err);
/* clear relaxed ordering enable */ /* clear relaxed ordering enable */
val16 &= ~IOAT_DEVCTRL_ROE; val16 &= ~IOAT_DEVCTRL_ROE;
err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16); err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
if (err) if (err)
return err; return pcibios_err_to_errno(err);
if (ioat_dma->cap & IOAT_CAP_DPS) if (ioat_dma->cap & IOAT_CAP_DPS)
writeb(ioat_pending_level + 1, writeb(ioat_pending_level + 1,

2
drivers/gpu/drm/qxl/qxl_dev.h
View File

@ -131,8 +131,6 @@ enum SpiceCursorType {
#pragma pack(push, 1) #pragma pack(push, 1)
#define REDHAT_PCI_VENDOR_ID 0x1b36
/* 0x100-0x11f reserved for spice, 0x1ff used for unstable work */ /* 0x100-0x11f reserved for spice, 0x1ff used for unstable work */
#define QXL_DEVICE_ID_STABLE 0x0100 #define QXL_DEVICE_ID_STABLE 0x0100

1
drivers/net/ethernet/rocker/rocker_hw.h
View File

@ -25,7 +25,6 @@ enum {
#define ROCKER_FP_PORTS_MAX 62 #define ROCKER_FP_PORTS_MAX 62
#define PCI_VENDOR_ID_REDHAT 0x1b36
#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
#define ROCKER_PCI_BAR0_SIZE 0x2000 #define ROCKER_PCI_BAR0_SIZE 0x2000

8
drivers/pci/access.c
View File

@ -405,7 +405,7 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
*val = 0; *val = 0;
if (pos & 1) if (pos & 1)
return -EINVAL; return PCIBIOS_BAD_REGISTER_NUMBER;
if (pcie_capability_reg_implemented(dev, pos)) { if (pcie_capability_reg_implemented(dev, pos)) {
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
@ -440,7 +440,7 @@ int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
*val = 0; *val = 0;
if (pos & 3) if (pos & 3)
return -EINVAL; return PCIBIOS_BAD_REGISTER_NUMBER;
if (pcie_capability_reg_implemented(dev, pos)) { if (pcie_capability_reg_implemented(dev, pos)) {
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
@ -465,7 +465,7 @@ EXPORT_SYMBOL(pcie_capability_read_dword);
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
{ {
if (pos & 1) if (pos & 1)
return -EINVAL; return PCIBIOS_BAD_REGISTER_NUMBER;
if (!pcie_capability_reg_implemented(dev, pos)) if (!pcie_capability_reg_implemented(dev, pos))
return 0; return 0;
@ -477,7 +477,7 @@ EXPORT_SYMBOL(pcie_capability_write_word);
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val) int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
{ {
if (pos & 3) if (pos & 3)
return -EINVAL; return PCIBIOS_BAD_REGISTER_NUMBER;
if (!pcie_capability_reg_implemented(dev, pos)) if (!pcie_capability_reg_implemented(dev, pos))
return 0; return 0;

2
drivers/pci/controller/dwc/pci-dra7xx.c
View File

@ -2,7 +2,7 @@
/* /*
* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
* *
* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
* *
* Authors: Kishon Vijay Abraham I <kishon@ti.com> * Authors: Kishon Vijay Abraham I <kishon@ti.com>
*/ */

2
drivers/pci/controller/dwc/pci-exynos.c
View File

@ -3,7 +3,7 @@
* PCIe host controller driver for Samsung Exynos SoCs * PCIe host controller driver for Samsung Exynos SoCs
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pci-imx6.c
View File

@ -3,7 +3,7 @@
* PCIe host controller driver for Freescale i.MX6 SoCs * PCIe host controller driver for Freescale i.MX6 SoCs
* *
* Copyright (C) 2013 Kosagi * Copyright (C) 2013 Kosagi
* http://www.kosagi.com * https://www.kosagi.com
* *
* Author: Sean Cross <xobs@kosagi.com> * Author: Sean Cross <xobs@kosagi.com>
*/ */

2
drivers/pci/controller/dwc/pci-keystone.c
View File

@ -3,7 +3,7 @@
* PCIe host controller driver for Texas Instruments Keystone SoCs * PCIe host controller driver for Texas Instruments Keystone SoCs
* *
* Copyright (C) 2013-2014 Texas Instruments., Ltd. * Copyright (C) 2013-2014 Texas Instruments., Ltd.
* http://www.ti.com * https://www.ti.com
* *
* Author: Murali Karicheri <m-karicheri2@ti.com> * Author: Murali Karicheri <m-karicheri2@ti.com>
* Implementation based on pci-exynos.c and pcie-designware.c * Implementation based on pci-exynos.c and pcie-designware.c

2
drivers/pci/controller/dwc/pcie-designware-host.c
View File

@ -3,7 +3,7 @@
* Synopsys DesignWare PCIe host controller driver * Synopsys DesignWare PCIe host controller driver
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pcie-designware.c
View File

@ -3,7 +3,7 @@
* Synopsys DesignWare PCIe host controller driver * Synopsys DesignWare PCIe host controller driver
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pcie-designware.h
View File

@ -3,7 +3,7 @@
* Synopsys DesignWare PCIe host controller driver * Synopsys DesignWare PCIe host controller driver
* *
* Copyright (C) 2013 Samsung Electronics Co., Ltd. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * https://www.samsung.com
* *
* Author: Jingoo Han <jg1.han@samsung.com> * Author: Jingoo Han <jg1.han@samsung.com>
*/ */

2
drivers/pci/controller/dwc/pcie-kirin.c
View File

@ -3,7 +3,7 @@
* PCIe host controller driver for Kirin Phone SoCs * PCIe host controller driver for Kirin Phone SoCs
* *
* Copyright (C) 2017 HiSilicon Electronics Co., Ltd. * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
* http://www.huawei.com * https://www.huawei.com
* *
* Author: Xiaowei Song <songxiaowei@huawei.com> * Author: Xiaowei Song <songxiaowei@huawei.com>
*/ */

50
drivers/pci/irq.c
View File

@ -6,61 +6,11 @@
* Copyright (C) 2017 Christoph Hellwig. * Copyright (C) 2017 Christoph Hellwig.
*/ */
#include <linux/acpi.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/export.h> #include <linux/export.h>
#include <linux/pci.h> #include <linux/pci.h>
static void pci_note_irq_problem(struct pci_dev *pdev, const char *reason)
{
struct pci_dev *parent = to_pci_dev(pdev->dev.parent);
pci_err(pdev, "Potentially misrouted IRQ (Bridge %s %04x:%04x)\n",
dev_name(&parent->dev), parent->vendor, parent->device);
pci_err(pdev, "%s\n", reason);
pci_err(pdev, "Please report to linux-kernel@vger.kernel.org\n");
WARN_ON(1);
}
/**
* pci_lost_interrupt - reports a lost PCI interrupt
* @pdev: device whose interrupt is lost
*
* The primary function of this routine is to report a lost interrupt
* in a standard way which users can recognise (instead of blaming the
* driver).
*
* Returns:
* a suggestion for fixing it (although the driver is not required to
* act on this).
*/
enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *pdev)
{
if (pdev->msi_enabled || pdev->msix_enabled) {
enum pci_lost_interrupt_reason ret;
if (pdev->msix_enabled) {
pci_note_irq_problem(pdev, "MSIX routing failure");
ret = PCI_LOST_IRQ_DISABLE_MSIX;
} else {
pci_note_irq_problem(pdev, "MSI routing failure");
ret = PCI_LOST_IRQ_DISABLE_MSI;
}
return ret;
}
#ifdef CONFIG_ACPI
if (!(acpi_disabled || acpi_noirq)) {
pci_note_irq_problem(pdev, "Potential ACPI misrouting please reboot with acpi=noirq");
/* currently no way to fix acpi on the fly */
return PCI_LOST_IRQ_DISABLE_ACPI;
}
#endif
pci_note_irq_problem(pdev, "unknown cause (not MSI or ACPI)");
return PCI_LOST_IRQ_NO_INFORMATION;
}
EXPORT_SYMBOL(pci_lost_interrupt);
/** /**
* pci_request_irq - allocate an interrupt line for a PCI device * pci_request_irq - allocate an interrupt line for a PCI device
* @dev: PCI device to operate on * @dev: PCI device to operate on

2
drivers/pci/pci-label.c
View File

@ -18,7 +18,7 @@
* the instance number and string from the type 41 record and exports * the instance number and string from the type 41 record and exports
* it to sysfs. * it to sysfs.
* *
* Please see http://linux.dell.com/files/biosdevname/ for more * Please see https://linux.dell.com/files/biosdevname/ for more
* information. * information.
*/ */

10
drivers/pci/pci.c
View File

@ -5708,6 +5708,7 @@ EXPORT_SYMBOL(pcie_get_readrq);
int pcie_set_readrq(struct pci_dev *dev, int rq) int pcie_set_readrq(struct pci_dev *dev, int rq)
{ {
u16 v; u16 v;
int ret;
if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
return -EINVAL; return -EINVAL;
@ -5726,8 +5727,10 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
v = (ffs(rq) - 8) << 12; v = (ffs(rq) - 8) << 12;
return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_READRQ, v); PCI_EXP_DEVCTL_READRQ, v);
return pcibios_err_to_errno(ret);
} }
EXPORT_SYMBOL(pcie_set_readrq); EXPORT_SYMBOL(pcie_set_readrq);
@ -5758,6 +5761,7 @@ EXPORT_SYMBOL(pcie_get_mps);
int pcie_set_mps(struct pci_dev *dev, int mps) int pcie_set_mps(struct pci_dev *dev, int mps)
{ {
u16 v; u16 v;
int ret;
if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
return -EINVAL; return -EINVAL;
@ -5767,8 +5771,10 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
return -EINVAL; return -EINVAL;
v <<= 5; v <<= 5;
return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_PAYLOAD, v); PCI_EXP_DEVCTL_PAYLOAD, v);
return pcibios_err_to_errno(ret);
} }
EXPORT_SYMBOL(pcie_set_mps); EXPORT_SYMBOL(pcie_set_mps);

2
drivers/pci/pcie/Kconfig
View File

@ -43,7 +43,7 @@ config PCIEAER_INJECT
error injection can fake almost all kinds of errors with the error injection can fake almost all kinds of errors with the
help of a user space helper tool aer-inject, which can be help of a user space helper tool aer-inject, which can be
gotten from: gotten from:
http://www.kernel.org/pub/linux/utils/pci/aer-inject/ https://www.kernel.org/pub/linux/utils/pci/aer-inject/
# #
# PCI Express ECRC # PCI Express ECRC

11
drivers/pci/pcie/aer.c
View File

@ -224,20 +224,25 @@ int pcie_aer_is_native(struct pci_dev *dev)
int pci_enable_pcie_error_reporting(struct pci_dev *dev) int pci_enable_pcie_error_reporting(struct pci_dev *dev)
{ {
int rc;
if (!pcie_aer_is_native(dev)) if (!pcie_aer_is_native(dev))
return -EIO; return -EIO;
return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
return pcibios_err_to_errno(rc);
} }
EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
int pci_disable_pcie_error_reporting(struct pci_dev *dev) int pci_disable_pcie_error_reporting(struct pci_dev *dev)
{ {
int rc;
if (!pcie_aer_is_native(dev)) if (!pcie_aer_is_native(dev))
return -EIO; return -EIO;
return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, rc = pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
PCI_EXP_AER_FLAGS); return pcibios_err_to_errno(rc);
} }
EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting); EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);

2
drivers/pci/pcie/aer_inject.c
View File

@ -6,7 +6,7 @@
* trigger various real hardware errors. Software based error * trigger various real hardware errors. Software based error
* injection can fake almost all kinds of errors with the help of a * injection can fake almost all kinds of errors with the help of a
* user space helper tool aer-inject, which can be gotten from: * user space helper tool aer-inject, which can be gotten from:
* http://www.kernel.org/pub/linux/utils/pci/aer-inject/ * https://www.kernel.org/pub/linux/utils/pci/aer-inject/
* *
* Copyright 2009 Intel Corporation. * Copyright 2009 Intel Corporation.
* Huang Ying <ying.huang@intel.com> * Huang Ying <ying.huang@intel.com>

18
drivers/pci/quirks.c
View File

@ -3549,7 +3549,7 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
* The device will throw a Link Down error on AER-capable systems and * The device will throw a Link Down error on AER-capable systems and
* regardless of AER, config space of the device is never accessible again * regardless of AER, config space of the device is never accessible again
* and typically causes the system to hang or reset when access is attempted. * and typically causes the system to hang or reset when access is attempted.
* http://www.spinics.net/lists/linux-pci/msg34797.html * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
*/ */
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
@ -4378,9 +4378,9 @@ static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
* redirect (CR) since all transactions are redirected to the upstream * redirect (CR) since all transactions are redirected to the upstream
* root complex. * root complex.
* *
* http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
* http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
* http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
* *
* 1002:4385 SBx00 SMBus Controller * 1002:4385 SBx00 SMBus Controller
* 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
@ -4620,11 +4620,11 @@ static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
* *
* 0x9d10-0x9d1b PCI Express Root port #{1-12} * 0x9d10-0x9d1b PCI Express Root port #{1-12}
* *
* [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
* [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
* [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
* [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
* [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
* [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
* [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
*/ */

2
drivers/pci/setup-bus.c
View File

@ -152,7 +152,7 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
if (!tmp) if (!tmp)
panic("pdev_sort_resources(): kmalloc() failed!\n"); panic("%s: kzalloc() failed!\n", __func__);
tmp->res = r; tmp->res = r;
tmp->dev = dev; tmp->dev = dev;

3
drivers/pci/setup-res.c
View File

@ -73,7 +73,8 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno)
/* /*
* Apparently some Matrox devices have ROM BARs that read * Apparently some Matrox devices have ROM BARs that read
* as zero when disabled, so don't update ROM BARs unless * as zero when disabled, so don't update ROM BARs unless
* they're enabled. See https://lkml.org/lkml/2005/8/30/138. * they're enabled. See
* https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
*/ */
if (!(res->flags & IORESOURCE_ROM_ENABLE)) if (!(res->flags & IORESOURCE_ROM_ENABLE))
return; return;

6
drivers/scsi/smartpqi/smartpqi_init.c
View File

@ -7423,8 +7423,12 @@ static int pqi_ctrl_init_resume(struct pqi_ctrl_info *ctrl_info)
static inline int pqi_set_pcie_completion_timeout(struct pci_dev *pci_dev, static inline int pqi_set_pcie_completion_timeout(struct pci_dev *pci_dev,
u16 timeout) u16 timeout)
{ {
return pcie_capability_clear_and_set_word(pci_dev, PCI_EXP_DEVCTL2, int rc;
rc = pcie_capability_clear_and_set_word(pci_dev, PCI_EXP_DEVCTL2,
PCI_EXP_DEVCTL2_COMP_TIMEOUT, timeout); PCI_EXP_DEVCTL2_COMP_TIMEOUT, timeout);
return pcibios_err_to_errno(rc);
} }
static int pqi_pci_init(struct pqi_ctrl_info *ctrl_info) static int pqi_pci_init(struct pqi_ctrl_info *ctrl_info)

7
include/linux/pci.h
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@ -1060,13 +1060,6 @@ void pci_sort_breadthfirst(void);
/* Generic PCI functions exported to card drivers */ /* Generic PCI functions exported to card drivers */
enum pci_lost_interrupt_reason {
PCI_LOST_IRQ_NO_INFORMATION = 0,
PCI_LOST_IRQ_DISABLE_MSI,
PCI_LOST_IRQ_DISABLE_MSIX,
PCI_LOST_IRQ_DISABLE_ACPI,
};
enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
int pci_find_capability(struct pci_dev *dev, int cap); int pci_find_capability(struct pci_dev *dev, int cap);
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
int pci_find_ext_capability(struct pci_dev *dev, int cap); int pci_find_ext_capability(struct pci_dev *dev, int cap);

2
include/linux/pci_ids.h
View File

@ -2585,6 +2585,8 @@
#define PCI_VENDOR_ID_ASMEDIA 0x1b21 #define PCI_VENDOR_ID_ASMEDIA 0x1b21
#define PCI_VENDOR_ID_REDHAT 0x1b36
#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36 #define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS 0x1c36
#define PCI_VENDOR_ID_CIRCUITCO 0x1cc8 #define PCI_VENDOR_ID_CIRCUITCO 0x1cc8

2
samples/vfio-mdev/mdpy-defs.h
View File

@ -9,7 +9,7 @@
*/ */
/* pci ids */ /* pci ids */
#define MDPY_PCI_VENDOR_ID 0x1b36 /* redhat */ #define MDPY_PCI_VENDOR_ID PCI_VENDOR_ID_REDHAT
#define MDPY_PCI_DEVICE_ID 0x000f #define MDPY_PCI_DEVICE_ID 0x000f
#define MDPY_PCI_SUBVENDOR_ID PCI_SUBVENDOR_ID_REDHAT_QUMRANET #define MDPY_PCI_SUBVENDOR_ID PCI_SUBVENDOR_ID_REDHAT_QUMRANET
#define MDPY_PCI_SUBDEVICE_ID PCI_SUBDEVICE_ID_QEMU #define MDPY_PCI_SUBDEVICE_ID PCI_SUBDEVICE_ID_QEMU