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arm64: dts: exynos: Swap clock order of sysmmu on Exynos5433

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dt-schema supports only order of names "aclk", "pclk".  Swap some sysmmu
definitions to make them compatible with schema.

Signed-off-by: Maciej Falkowski <m.falkowski@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Maciej Falkowski 2019-09-19 15:50:53 +02:00 committed by Krzysztof Kozlowski
parent bed903167a
commit 0d92c191ad
1 changed files with 27 additions and 27 deletions
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54
arch/arm64/boot/dts/exynos/exynos5433.dtsi
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@ -1179,9 +1179,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13a00000 0x1000>; reg = <0x13a00000 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_SMMU_DECON0X>; <&cmu_disp CLK_PCLK_SMMU_DECON0X>;
power-domains = <&pd_disp>; power-domains = <&pd_disp>;
#iommu-cells = <0>; #iommu-cells = <0>;
}; };
@ -1190,9 +1190,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13a10000 0x1000>; reg = <0x13a10000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
<&cmu_disp CLK_ACLK_SMMU_DECON1X>; <&cmu_disp CLK_PCLK_SMMU_DECON1X>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_disp>; power-domains = <&pd_disp>;
}; };
@ -1201,9 +1201,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13a20000 0x1000>; reg = <0x13a20000 0x1000>;
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>, clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
<&cmu_disp CLK_ACLK_SMMU_TV0X>; <&cmu_disp CLK_PCLK_SMMU_TV0X>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_disp>; power-domains = <&pd_disp>;
}; };
@ -1212,9 +1212,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x13a30000 0x1000>; reg = <0x13a30000 0x1000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>, clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
<&cmu_disp CLK_ACLK_SMMU_TV1X>; <&cmu_disp CLK_PCLK_SMMU_TV1X>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_disp>; power-domains = <&pd_disp>;
}; };
@ -1256,9 +1256,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x15040000 0x1000>; reg = <0x15040000 0x1000>;
interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>, clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
<&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>; <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_mscl>; power-domains = <&pd_mscl>;
}; };
@ -1267,9 +1267,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x15050000 0x1000>; reg = <0x15050000 0x1000>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>, clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
<&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>; <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_mscl>; power-domains = <&pd_mscl>;
}; };
@ -1278,9 +1278,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x15060000 0x1000>; reg = <0x15060000 0x1000>;
interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>, clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
<&cmu_mscl CLK_ACLK_SMMU_JPEG>; <&cmu_mscl CLK_PCLK_SMMU_JPEG>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_mscl>; power-domains = <&pd_mscl>;
}; };
@ -1289,9 +1289,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x15200000 0x1000>; reg = <0x15200000 0x1000>;
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>, clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_0>; <&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_mfc>; power-domains = <&pd_mfc>;
}; };
@ -1300,9 +1300,9 @@
compatible = "samsung,exynos-sysmmu"; compatible = "samsung,exynos-sysmmu";
reg = <0x15210000 0x1000>; reg = <0x15210000 0x1000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk"; clock-names = "aclk", "pclk";
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>, clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_1>; <&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
#iommu-cells = <0>; #iommu-cells = <0>;
power-domains = <&pd_mfc>; power-domains = <&pd_mfc>;
}; };