riscv: gcov: enable gcov for RISC-V
This patch enables GCOV code coverage measurement on RISC-V. Lightly tested on QEMU and Hifive Unleashed board, seems to work as expected. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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@ -23,7 +23,7 @@
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| openrisc: | TODO |
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| openrisc: | TODO |
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| parisc: | TODO |
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| parisc: | TODO |
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| powerpc: | ok |
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| powerpc: | ok |
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| riscv: | TODO |
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| riscv: | ok |
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| s390: | ok |
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| s390: | ok |
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| sh: | ok |
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| sh: | ok |
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| sparc: | TODO |
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| sparc: | TODO |
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@ -64,6 +64,7 @@ config RISCV
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select SPARSEMEM_STATIC if 32BIT
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select SPARSEMEM_STATIC if 32BIT
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select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
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select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
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select HAVE_ARCH_MMAP_RND_BITS if MMU
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select HAVE_ARCH_MMAP_RND_BITS if MMU
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select ARCH_HAS_GCOV_PROFILE_ALL
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config ARCH_MMAP_RND_BITS_MIN
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config ARCH_MMAP_RND_BITS_MIN
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default 18 if 64BIT
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default 18 if 64BIT
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