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drm/amdgpu: correct MEC number for gfx11 APUs

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There is only one MEC on these APUs.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x
This commit is contained in:
Lang Yu 2023-01-11 09:52:11 +08:00 committed by Alex Deucher
parent e433adc60f
commit 0ddadc3a22
1 changed files with 9 additions and 2 deletions
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11
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
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@ -1287,10 +1287,8 @@ static int gfx_v11_0_sw_init(void *handle)
switch (adev->ip_versions[GC_HWIP][0]) { switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3): case IP_VERSION(11, 0, 3):
case IP_VERSION(11, 0, 4):
adev->gfx.me.num_me = 1; adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.me.num_queue_per_pipe = 1;
@ -1298,6 +1296,15 @@ static int gfx_v11_0_sw_init(void *handle)
adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 4; adev->gfx.mec.num_queue_per_pipe = 4;
break; break;
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 4):
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 4;
break;
default: default:
adev->gfx.me.num_me = 1; adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_pipe_per_me = 1;