iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'remotes/lorenzo/pci/mvebu'

Browse Source 
- Implement pci_remap_iospace() for ARM so mvebu can use
  devm_pci_remap_iospace() instead of the previous ARM-specific
  pci_ioremap_io() interface (Pali Rohár)

- Use the standard pci_host_probe() instead of the device-specific
  mvebu_pci_host_probe() (Pali Rohár)

- Replace all uses of ARM-specific pci_ioremap_io() with the
  ARM implementation of the standard pci_remap_iospace() interface and
  remove pci_ioremap_io() (Pali Rohár)

- Skip initializing invalid Root Ports (Pali Rohár)

- Check for errors from pci_bridge_emul_init() (Pali Rohár)

- Ignore any bridges at non-zero function numbers (Pali Rohár)

- Return ~0 data for invalid config read size (Pali Rohár)

- Disallow mapping interrupts on emulated bridges (Pali Rohár)

- Clear Root Port Memory & I/O Space Enable and Bus Master Enable at
  initialization (Pali Rohár)

- Make type bits in Root Port I/O Base register read-only (Pali Rohár)

- Disable Root Port windows when base/limit set to invalid values (Pali
  Rohár)

- Set controller to Root Complex mode (Pali Rohár)

- Set Root Port Class Code to PCI Bridge (Pali Rohár)

- Update emulated Root Port secondary bus numbers to better reflect the
  actual topology (Pali Rohár)

- Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so
  pci_reset_secondary_bus() can reset connected devices (Pali Rohár)

- Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root Ports
  (Pali Rohár)

- Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports (Pali
  Rohár)

- Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on Armada
  XP and newer devices (Pali Rohár)

- Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module (Pali
  Rohár)

- Add support for compiling as a module (Pali Rohár)

* remotes/lorenzo/pci/mvebu:
  PCI: mvebu: Add support for compiling driver as module
  bus: mvebu-mbus: Export symbols for public API window functions
  PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on emulated bridge
  PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridge
  PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridge
  PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
  PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge
  PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge
  PCI: mvebu: Setup PCIe controller to Root Complex mode
  PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers
  PCI: mvebu: Do not modify PCI IO type bits in conf_write
  PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge
  PCI: mvebu: Disallow mapping interrupts on emulated bridges
  PCI: mvebu: Handle invalid size of read config request
  PCI: mvebu: Check that PCI bridge specified in DT has function number zero
  PCI: mvebu: Check for errors from pci_bridge_emul_init() call
  PCI: mvebu: Check for valid ports
  arm: ioremap: Remove unused ARM-specific function pci_ioremap_io()
  arm: ioremap: Replace pci_ioremap_io() usage by pci_remap_iospace()
  PCI: mvebu: Remove custom mvebu_pci_host_probe() function
  PCI: mvebu: Replace pci_ioremap_io() usage by devm_pci_remap_iospace()
  arm: ioremap: Implement standard PCI function pci_remap_iospace()
This commit is contained in:
Bjorn Helgaas 2022-01-13 09:57:49 -06:00
commit 0de15dbbd6
10 changed files with 444 additions and 153 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/include/asm/io.h
View File

@ -180,7 +180,10 @@ void pci_ioremap_set_mem_type(int mem_type);
static inline void pci_ioremap_set_mem_type(int mem_type) {}
#endif
extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
struct resource;
#define pci_remap_iospace pci_remap_iospace
int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
/*
* PCI configuration space mapping function.

9
arch/arm/mach-dove/pcie.c
View File

@ -38,6 +38,7 @@ static int num_pcie_ports;
static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct pcie_port *pp;
struct resource realio;
if (nr >= num_pcie_ports)
return 0;
@ -53,10 +54,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
orion_pcie_setup(pp->base);
if (pp->index == 0)
pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
else
pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
realio.start = sys->busnr * SZ_64K;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
DOVE_PCIE1_IO_PHYS_BASE);
/*
* IORESOURCE_MEM

5
arch/arm/mach-iop32x/pci.c
View File

@ -185,6 +185,7 @@ iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
struct resource realio;
if (nr != 0)
return 0;
@ -206,7 +207,9 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
realio.start = 0;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA);
return 1;
}

5
arch/arm/mach-mv78xx0/pcie.c
View File

@ -101,6 +101,7 @@ static void __init mv78xx0_pcie_preinit(void)
static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct pcie_port *pp;
struct resource realio;
if (nr >= num_pcie_ports)
return 0;
@ -115,7 +116,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
orion_pcie_setup(pp->base);
pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
realio.start = nr * SZ_64K;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr));
pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);

10
arch/arm/mach-orion5x/pci.c
View File

@ -142,6 +142,7 @@ static struct pci_ops pcie_ops = {
static int __init pcie_setup(struct pci_sys_data *sys)
{
struct resource *res;
struct resource realio;
int dev;
/*
@ -164,7 +165,9 @@ static int __init pcie_setup(struct pci_sys_data *sys)
pcie_ops.read = pcie_rd_conf_wa;
}
pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
realio.start = sys->busnr * SZ_64K;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE);
/*
* Request resources.
@ -466,6 +469,7 @@ static void __init orion5x_setup_pci_wins(void)
static int __init pci_setup(struct pci_sys_data *sys)
{
struct resource *res;
struct resource realio;
/*
* Point PCI unit MBUS decode windows to DRAM space.
@ -482,7 +486,9 @@ static int __init pci_setup(struct pci_sys_data *sys)
*/
orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
realio.start = sys->busnr * SZ_64K;
realio.end = realio.start + SZ_64K - 1;
pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE);
/*
* Request resources

16
arch/arm/mm/ioremap.c
View File

@ -459,16 +459,20 @@ void pci_ioremap_set_mem_type(int mem_type)
pci_ioremap_mem_type = mem_type;
}
int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
{
BUG_ON(offset + SZ_64K - 1 > IO_SPACE_LIMIT);
unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
PCI_IO_VIRT_BASE + offset + SZ_64K,
phys_addr,
if (!(res->flags & IORESOURCE_IO))
return -EINVAL;
if (res->end > IO_SPACE_LIMIT)
return -EINVAL;
return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
__pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte));
}
EXPORT_SYMBOL_GPL(pci_ioremap_io);
EXPORT_SYMBOL(pci_remap_iospace);
void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)
{

5
drivers/bus/mvebu-mbus.c
View File

@ -914,6 +914,7 @@ int mvebu_mbus_add_window_remap_by_id(unsigned int target,
return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
}
EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_remap_by_id);
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
phys_addr_t base, size_t size)
@ -921,6 +922,7 @@ int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
size, MVEBU_MBUS_NO_REMAP);
}
EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_by_id);
int mvebu_mbus_del_window(phys_addr_t base, size_t size)
{
@ -933,6 +935,7 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size)
mvebu_mbus_disable_window(&mbus_state, win);
return 0;
}
EXPORT_SYMBOL_GPL(mvebu_mbus_del_window);
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
{
@ -940,6 +943,7 @@ void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
return;
*res = mbus_state.pcie_mem_aperture;
}
EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_mem_aperture);
void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
{
@ -947,6 +951,7 @@ void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
return;
*res = mbus_state.pcie_io_aperture;
}
EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture);
int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
{

2
drivers/pci/controller/Kconfig
View File

@ -4,7 +4,7 @@ menu "PCI controller drivers"
depends on PCI
config PCI_MVEBU
bool "Marvell EBU PCIe controller"
tristate "Marvell EBU PCIe controller"
depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
depends on MVEBU_MBUS
depends on ARM

534
drivers/pci/controller/pci-mvebu.c
View File

@ -6,6 +6,7 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/clk.h>
#include <linux/delay.h>
@ -51,10 +52,14 @@
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_INT_CAUSE_OFF 0x1900
#define PCIE_INT_PM_PME BIT(28)
#define PCIE_MASK_OFF 0x1910
#define PCIE_MASK_ENABLE_INTS 0x0f000000
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE 0x0001
#define PCIE_CTRL_RC_MODE BIT(1)
#define PCIE_CTRL_MASTER_HOT_RESET BIT(24)
#define PCIE_STAT_OFF 0x1a04
#define PCIE_STAT_BUS 0xff00
#define PCIE_STAT_DEV 0x1f0000
@ -125,6 +130,11 @@ static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
}
static u8 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port)
{
return (mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_BUS) >> 8;
}
static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
{
u32 stat;
@ -145,6 +155,30 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
mvebu_writel(port, stat, PCIE_STAT_OFF);
}
static void mvebu_pcie_disable_wins(struct mvebu_pcie_port *port)
{
int i;
mvebu_writel(port, 0, PCIE_BAR_LO_OFF(0));
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
for (i = 1; i < 3; i++) {
mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
}
for (i = 0; i < 5; i++) {
mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
}
mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
}
/*
* Setup PCIE BARs and Address Decode Wins:
* BAR[0] -> internal registers (needed for MSI)
@ -161,21 +195,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
dram = mv_mbus_dram_info();
/* First, disable and clear BARs and windows. */
for (i = 1; i < 3; i++) {
mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
}
for (i = 0; i < 5; i++) {
mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
}
mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
mvebu_pcie_disable_wins(port);
/* Setup windows for DDR banks. Count total DDR size on the fly. */
size = 0;
@ -213,18 +233,47 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
{
u32 cmd, mask;
u32 ctrl, cmd, dev_rev, mask;
/* Setup PCIe controller to Root Complex mode. */
ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
ctrl |= PCIE_CTRL_RC_MODE;
mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
/* Disable Root Bridge I/O space, memory space and bus mastering. */
cmd = mvebu_readl(port, PCIE_CMD_OFF);
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
mvebu_writel(port, cmd, PCIE_CMD_OFF);
/*
* Change Class Code of PCI Bridge device to PCI Bridge (0x6004)
* because default value is Memory controller (0x5080).
*
* Note that this mvebu PCI Bridge does not have compliant Type 1
* Configuration Space. Header Type is reported as Type 0 and it
* has format of Type 0 config space.
*
* Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
* have the same format in Marvell's specification as in PCIe
* specification, but their meaning is totally different and they do
* different things: they are aliased into internal mvebu registers
* (e.g. PCIE_BAR_LO_OFF) and these should not be changed or
* reconfigured by pci device drivers.
*
* Therefore driver uses emulation of PCI Bridge which emulates
* access to configuration space via internal mvebu registers or
* emulated configuration buffer. Driver access these PCI Bridge
* directly for simplification, but these registers can be accessed
* also via standard mvebu way for accessing PCI config space.
*/
dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF);
dev_rev &= ~0xffffff00;
dev_rev |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF);
/* Point PCIe unit MBUS decode windows to DRAM space. */
mvebu_pcie_setup_wins(port);
/* Master + slave enable. */
cmd = mvebu_readl(port, PCIE_CMD_OFF);
cmd |= PCI_COMMAND_IO;
cmd |= PCI_COMMAND_MEMORY;
cmd |= PCI_COMMAND_MASTER;
mvebu_writel(port, cmd, PCIE_CMD_OFF);
/* Enable interrupt lines A-D. */
mask = mvebu_readl(port, PCIE_MASK_OFF);
mask |= PCIE_MASK_ENABLE_INTS;
@ -250,6 +299,9 @@ static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
case 4:
*val = readl_relaxed(conf_data);
break;
default:
*val = 0xffffffff;
return PCIBIOS_BAD_REGISTER_NUMBER;
}
return PCIBIOS_SUCCESSFUL;
@ -303,7 +355,7 @@ static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
* areas each having a power of two size. We start from the largest
* one (i.e highest order bit set in the size).
*/
static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
static int mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
unsigned int target, unsigned int attribute,
phys_addr_t base, size_t size,
phys_addr_t remap)
@ -324,7 +376,7 @@ static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
&base, &end, ret);
mvebu_pcie_del_windows(port, base - size_mapped,
size_mapped);
return;
return ret;
}
size -= sz;
@ -333,16 +385,20 @@ static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
if (remap != MVEBU_MBUS_NO_REMAP)
remap += sz;
}
return 0;
}
static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
static int mvebu_pcie_set_window(struct mvebu_pcie_port *port,
unsigned int target, unsigned int attribute,
const struct mvebu_pcie_window *desired,
struct mvebu_pcie_window *cur)
{
int ret;
if (desired->base == cur->base && desired->remap == cur->remap &&
desired->size == cur->size)
return;
return 0;
if (cur->size != 0) {
mvebu_pcie_del_windows(port, cur->base, cur->size);
@ -357,31 +413,35 @@ static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
}
if (desired->size == 0)
return;
return 0;
ret = mvebu_pcie_add_windows(port, target, attribute, desired->base,
desired->size, desired->remap);
if (ret) {
cur->size = 0;
cur->base = 0;
return ret;
}
mvebu_pcie_add_windows(port, target, attribute, desired->base,
desired->size, desired->remap);
*cur = *desired;
return 0;
}
static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
static int mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
{
struct mvebu_pcie_window desired = {};
struct pci_bridge_emul_conf *conf = &port->bridge.conf;
/* Are the new iobase/iolimit values invalid? */
if (conf->iolimit < conf->iobase ||
conf->iolimitupper < conf->iobaseupper ||
!(conf->command & PCI_COMMAND_IO)) {
mvebu_pcie_set_window(port, port->io_target, port->io_attr,
&desired, &port->iowin);
return;
}
conf->iolimitupper < conf->iobaseupper)
return mvebu_pcie_set_window(port, port->io_target, port->io_attr,
&desired, &port->iowin);
if (!mvebu_has_ioport(port)) {
dev_WARN(&port->pcie->pdev->dev,
"Attempt to set IO when IO is disabled\n");
return;
return -EOPNOTSUPP;
}
/*
@ -399,22 +459,19 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
desired.remap) +
1;
mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
&port->iowin);
return mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
&port->iowin);
}
static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
static int mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
{
struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
struct pci_bridge_emul_conf *conf = &port->bridge.conf;
/* Are the new membase/memlimit values invalid? */
if (conf->memlimit < conf->membase ||
!(conf->command & PCI_COMMAND_MEMORY)) {
mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
&desired, &port->memwin);
return;
}
if (conf->memlimit < conf->membase)
return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
&desired, &port->memwin);
/*
* We read the PCI-to-PCI bridge emulated registers, and
@ -426,8 +483,56 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) -
desired.base + 1;
mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
&port->memwin);
return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
&port->memwin);
}
static pci_bridge_emul_read_status_t
mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
int reg, u32 *value)
{
struct mvebu_pcie_port *port = bridge->data;
switch (reg) {
case PCI_COMMAND:
*value = mvebu_readl(port, PCIE_CMD_OFF);
break;
case PCI_PRIMARY_BUS: {
/*
* From the whole 32bit register we support reading from HW only
* secondary bus number which is mvebu local bus number.
* Other bits are retrieved only from emulated config buffer.
*/
__le32 *cfgspace = (__le32 *)&bridge->conf;
u32 val = le32_to_cpu(cfgspace[PCI_PRIMARY_BUS / 4]);
val &= ~0xff00;
val |= mvebu_pcie_get_local_bus_nr(port) << 8;
*value = val;
break;
}
case PCI_INTERRUPT_LINE: {
/*
* From the whole 32bit register we support reading from HW only
* one bit: PCI_BRIDGE_CTL_BUS_RESET.
* Other bits are retrieved only from emulated config buffer.
*/
__le32 *cfgspace = (__le32 *)&bridge->conf;
u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
if (mvebu_readl(port, PCIE_CTRL_OFF) & PCIE_CTRL_MASTER_HOT_RESET)
val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
else
val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
*value = val;
break;
}
default:
return PCI_BRIDGE_EMUL_NOT_HANDLED;
}
return PCI_BRIDGE_EMUL_HANDLED;
}
static pci_bridge_emul_read_status_t
@ -442,9 +547,7 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
break;
case PCI_EXP_DEVCTL:
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL) &
~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
break;
case PCI_EXP_LNKCAP:
@ -468,6 +571,18 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
*value = mvebu_readl(port, PCIE_RC_RTSTA);
break;
case PCI_EXP_DEVCAP2:
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP2);
break;
case PCI_EXP_DEVCTL2:
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
break;
case PCI_EXP_LNKCTL2:
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
break;
default:
return PCI_BRIDGE_EMUL_NOT_HANDLED;
}
@ -484,39 +599,62 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
switch (reg) {
case PCI_COMMAND:
{
if (!mvebu_has_ioport(port))
conf->command &= ~PCI_COMMAND_IO;
if ((old ^ new) & PCI_COMMAND_IO)
mvebu_pcie_handle_iobase_change(port);
if ((old ^ new) & PCI_COMMAND_MEMORY)
mvebu_pcie_handle_membase_change(port);
if (!mvebu_has_ioport(port)) {
conf->command = cpu_to_le16(
le16_to_cpu(conf->command) & ~PCI_COMMAND_IO);
new &= ~PCI_COMMAND_IO;
}
mvebu_writel(port, new, PCIE_CMD_OFF);
break;
}
case PCI_IO_BASE:
/*
* We keep bit 1 set, it is a read-only bit that
* indicates we support 32 bits addressing for the
* I/O
*/
conf->iobase |= PCI_IO_RANGE_TYPE_32;
conf->iolimit |= PCI_IO_RANGE_TYPE_32;
mvebu_pcie_handle_iobase_change(port);
if ((mask & 0xffff) && mvebu_pcie_handle_iobase_change(port)) {
/* On error disable IO range */
conf->iobase &= ~0xf0;
conf->iolimit &= ~0xf0;
conf->iobaseupper = cpu_to_le16(0x0000);
conf->iolimitupper = cpu_to_le16(0x0000);
if (mvebu_has_ioport(port))
conf->iobase |= 0xf0;
}
break;
case PCI_MEMORY_BASE:
mvebu_pcie_handle_membase_change(port);
if (mvebu_pcie_handle_membase_change(port)) {
/* On error disable mem range */
conf->membase = cpu_to_le16(le16_to_cpu(conf->membase) & ~0xfff0);
conf->memlimit = cpu_to_le16(le16_to_cpu(conf->memlimit) & ~0xfff0);
conf->membase = cpu_to_le16(le16_to_cpu(conf->membase) | 0xfff0);
}
break;
case PCI_IO_BASE_UPPER16:
mvebu_pcie_handle_iobase_change(port);
if (mvebu_pcie_handle_iobase_change(port)) {
/* On error disable IO range */
conf->iobase &= ~0xf0;
conf->iolimit &= ~0xf0;
conf->iobaseupper = cpu_to_le16(0x0000);
conf->iolimitupper = cpu_to_le16(0x0000);
if (mvebu_has_ioport(port))
conf->iobase |= 0xf0;
}
break;
case PCI_PRIMARY_BUS:
mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
if (mask & 0xff00)
mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
break;
case PCI_INTERRUPT_LINE:
if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
ctrl |= PCIE_CTRL_MASTER_HOT_RESET;
else
ctrl &= ~PCIE_CTRL_MASTER_HOT_RESET;
mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
}
break;
default:
@ -532,13 +670,6 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
switch (reg) {
case PCI_EXP_DEVCTL:
/*
* Armada370 data says these bits must always
* be zero when in root complex mode.
*/
new &= ~(PCI_EXP_DEVCTL_URRE | PCI_EXP_DEVCTL_FERE |
PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_CERE);
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
break;
@ -555,12 +686,31 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
break;
case PCI_EXP_RTSTA:
mvebu_writel(port, new, PCIE_RC_RTSTA);
/*
* PME Status bit in Root Status Register (PCIE_RC_RTSTA)
* is read-only and can be cleared only by writing 0b to the
* Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). So
* clear PME via Interrupt Cause.
*/
if (new & PCI_EXP_RTSTA_PME)
mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF);
break;
case PCI_EXP_DEVCTL2:
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
break;
case PCI_EXP_LNKCTL2:
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
break;
default:
break;
}
}
static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
.read_base = mvebu_pci_bridge_emul_base_conf_read,
.write_base = mvebu_pci_bridge_emul_base_conf_write,
.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
@ -570,7 +720,7 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
* Initialize the configuration space of the PCI-to-PCI bridge
* associated with the given PCIe interface.
*/
static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
{
struct pci_bridge_emul *bridge = &port->bridge;
@ -589,7 +739,7 @@ static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
bridge->data = port;
bridge->ops = &mvebu_pci_bridge_emul_ops;
pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
return pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
}
static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
@ -606,6 +756,9 @@ static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
for (i = 0; i < pcie->nports; i++) {
struct mvebu_pcie_port *port = &pcie->ports[i];
if (!port->base)
continue;
if (bus->number == 0 && port->devfn == devfn)
return port;
if (bus->number != 0 &&
@ -680,6 +833,15 @@ static struct pci_ops mvebu_pcie_ops = {
.write = mvebu_pcie_wr_conf,
};
static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
/* Interrupt support on mvebu emulated bridges is not implemented yet */
if (dev->bus->number == 0)
return 0; /* Proper return code 0 == NO_IRQ */
return of_irq_parse_and_map_pci(dev, slot, pin);
}
static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
const struct resource *res,
resource_size_t start,
@ -781,6 +943,8 @@ static int mvebu_pcie_suspend(struct device *dev)
pcie = dev_get_drvdata(dev);
for (i = 0; i < pcie->nports; i++) {
struct mvebu_pcie_port *port = pcie->ports + i;
if (!port->base)
continue;
port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
}
@ -795,6 +959,8 @@ static int mvebu_pcie_resume(struct device *dev)
pcie = dev_get_drvdata(dev);
for (i = 0; i < pcie->nports; i++) {
struct mvebu_pcie_port *port = pcie->ports + i;
if (!port->base)
continue;
mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
mvebu_pcie_setup_hw(port);
}
@ -838,6 +1004,11 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
port->devfn = of_pci_get_devfn(child);
if (port->devfn < 0)
goto skip;
if (PCI_FUNC(port->devfn) != 0) {
dev_err(dev, "%s: invalid function number, must be zero\n",
port->name);
goto skip;
}
ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
&port->mem_target, &port->mem_attr);
@ -992,6 +1163,10 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
resource_size(&pcie->io) - 1);
pcie->realio.name = "PCI I/O";
ret = devm_pci_remap_iospace(dev, &pcie->realio, pcie->io.start);
if (ret)
return ret;
pci_add_resource(&bridge->windows, &pcie->realio);
ret = devm_request_resource(dev, &ioport_resource, &pcie->realio);
if (ret)
@ -1001,54 +1176,6 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
return 0;
}
/*
* This is a copy of pci_host_probe(), except that it does the I/O
* remap as the last step, once we are sure we won't fail.
*
* It should be removed once the I/O remap error handling issue has
* been sorted out.
*/
static int mvebu_pci_host_probe(struct pci_host_bridge *bridge)
{
struct mvebu_pcie *pcie;
struct pci_bus *bus, *child;
int ret;
ret = pci_scan_root_bus_bridge(bridge);
if (ret < 0) {
dev_err(bridge->dev.parent, "Scanning root bridge failed");
return ret;
}
pcie = pci_host_bridge_priv(bridge);
if (resource_size(&pcie->io) != 0) {
unsigned int i;
for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
pci_ioremap_io(i, pcie->io.start + i);
}
bus = bridge->bus;
/*
* We insert PCI resources into the iomem_resource and
* ioport_resource trees in either pci_bus_claim_resources()
* or pci_bus_assign_resources().
*/
if (pci_has_flag(PCI_PROBE_ONLY)) {
pci_bus_claim_resources(bus);
} else {
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
}
pci_bus_add_devices(bus);
return 0;
}
static int mvebu_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -1112,9 +1239,93 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
continue;
}
ret = mvebu_pci_bridge_emul_init(port);
if (ret < 0) {
dev_err(dev, "%s: cannot init emulated bridge\n",
port->name);
devm_iounmap(dev, port->base);
port->base = NULL;
mvebu_pcie_powerdown(port);
continue;
}
/*
* PCIe topology exported by mvebu hw is quite complicated. In
* reality has something like N fully independent host bridges
* where each host bridge has one PCIe Root Port (which acts as
* PCI Bridge device). Each host bridge has its own independent
* internal registers, independent access to PCI config space,
* independent interrupt lines, independent window and memory
* access configuration. But additionally there is some kind of
* peer-to-peer support between PCIe devices behind different
* host bridges limited just to forwarding of memory and I/O
* transactions (forwarding of error messages and config cycles
* is not supported). So we could say there are N independent
* PCIe Root Complexes.
*
* For this kind of setup DT should have been structured into
* N independent PCIe controllers / host bridges. But instead
* structure in past was defined to put PCIe Root Ports of all
* host bridges into one bus zero, like in classic multi-port
* Root Complex setup with just one host bridge.
*
* This means that pci-mvebu.c driver provides "virtual" bus 0
* on which registers all PCIe Root Ports (PCI Bridge devices)
* specified in DT by their BDF addresses and virtually routes
* PCI config access of each PCI bridge device to specific PCIe
* host bridge.
*
* Normally PCI Bridge should choose between Type 0 and Type 1
* config requests based on primary and secondary bus numbers
* configured on the bridge itself. But because mvebu PCI Bridge
* does not have registers for primary and secondary bus numbers
* in its config space, it determinates type of config requests
* via its own custom way.
*
* There are two options how mvebu determinate type of config
* request.
*
* 1. If Secondary Bus Number Enable bit is not set or is not
* available (applies for pre-XP PCIe controllers) then Type 0
* is used if target bus number equals Local Bus Number (bits
* [15:8] in register 0x1a04) and target device number differs
* from Local Device Number (bits [20:16] in register 0x1a04).
* Type 1 is used if target bus number differs from Local Bus
* Number. And when target bus number equals Local Bus Number
* and target device equals Local Device Number then request is
* routed to Local PCI Bridge (PCIe Root Port).
*
* 2. If Secondary Bus Number Enable bit is set (bit 7 in
* register 0x1a2c) then mvebu hw determinate type of config
* request like compliant PCI Bridge based on primary bus number
* which is configured via Local Bus Number (bits [15:8] in
* register 0x1a04) and secondary bus number which is configured
* via Secondary Bus Number (bits [7:0] in register 0x1a2c).
* Local PCI Bridge (PCIe Root Port) is available on primary bus
* as device with Local Device Number (bits [20:16] in register
* 0x1a04).
*
* Secondary Bus Number Enable bit is disabled by default and
* option 2. is not available on pre-XP PCIe controllers. Hence
* this driver always use option 1.
*
* Basically it means that primary and secondary buses shares
* one virtual number configured via Local Bus Number bits and
* Local Device Number bits determinates if accessing primary
* or secondary bus. Set Local Device Number to 1 and redirect
* all writes of PCI Bridge Secondary Bus Number register to
* Local Bus Number (bits [15:8] in register 0x1a04).
*
* So when accessing devices on buses behind secondary bus
* number it would work correctly. And also when accessing
* device 0 at secondary bus number via config space would be
* correctly routed to secondary bus. Due to issues described
* in mvebu_pcie_setup_hw(), PCI Bridges at primary bus (zero)
* are not accessed directly via PCI config space but rarher
* indirectly via kernel emulated PCI bridge driver.
*/
mvebu_pcie_setup_hw(port);
mvebu_pcie_set_local_dev_nr(port, 1);
mvebu_pci_bridge_emul_init(port);
mvebu_pcie_set_local_dev_nr(port, 0);
}
pcie->nports = i;
@ -1122,8 +1333,55 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
bridge->sysdata = pcie;
bridge->ops = &mvebu_pcie_ops;
bridge->align_resource = mvebu_pcie_align_resource;
bridge->map_irq = mvebu_pcie_map_irq;
return mvebu_pci_host_probe(bridge);
return pci_host_probe(bridge);
}
static int mvebu_pcie_remove(struct platform_device *pdev)
{
struct mvebu_pcie *pcie = platform_get_drvdata(pdev);
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
u32 cmd;
int i;
/* Remove PCI bus with all devices. */
pci_lock_rescan_remove();
pci_stop_root_bus(bridge->bus);
pci_remove_root_bus(bridge->bus);
pci_unlock_rescan_remove();
for (i = 0; i < pcie->nports; i++) {
struct mvebu_pcie_port *port = &pcie->ports[i];
if (!port->base)
continue;
/* Disable Root Bridge I/O space, memory space and bus mastering. */
cmd = mvebu_readl(port, PCIE_CMD_OFF);
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
mvebu_writel(port, cmd, PCIE_CMD_OFF);
/* Mask all interrupt sources. */
mvebu_writel(port, 0, PCIE_MASK_OFF);
/* Free config space for emulated root bridge. */
pci_bridge_emul_cleanup(&port->bridge);
/* Disable and clear BARs and windows. */
mvebu_pcie_disable_wins(port);
/* Delete PCIe IO and MEM windows. */
if (port->iowin.size)
mvebu_pcie_del_windows(port, port->iowin.base, port->iowin.size);
if (port->memwin.size)
mvebu_pcie_del_windows(port, port->memwin.base, port->memwin.size);
/* Power down card and disable clocks. Must be the last step. */
mvebu_pcie_powerdown(port);
}
return 0;
}
static const struct of_device_id mvebu_pcie_of_match_table[] = {
@ -1142,10 +1400,14 @@ static struct platform_driver mvebu_pcie_driver = {
.driver = {
.name = "mvebu-pcie",
.of_match_table = mvebu_pcie_of_match_table,
/* driver unloading/unbinding currently not supported */
.suppress_bind_attrs = true,
.pm = &mvebu_pcie_pm_ops,
},
.probe = mvebu_pcie_probe,
.remove = mvebu_pcie_remove,
};
builtin_platform_driver(mvebu_pcie_driver);
module_platform_driver(mvebu_pcie_driver);
MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@bootlin.com>");
MODULE_AUTHOR("Pali Rohár <pali@kernel.org>");
MODULE_DESCRIPTION("Marvell EBU PCIe controller");
MODULE_LICENSE("GPL v2");

6
drivers/pcmcia/at91_cf.c
View File

@ -20,6 +20,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/regmap.h>
#include <pcmcia/ss.h>
@ -230,6 +231,7 @@ static int at91_cf_probe(struct platform_device *pdev)
struct at91_cf_socket *cf;
struct at91_cf_data *board;
struct resource *io;
struct resource realio;
int status;
board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
@ -307,7 +309,9 @@ static int at91_cf_probe(struct platform_device *pdev)
* io_offset is set to 0x10000 to avoid the check in static_find_io().
* */
cf->socket.io_offset = 0x10000;
status = pci_ioremap_io(0x10000, cf->phys_baseaddr + CF_IO_PHYS);
realio.start = cf->socket.io_offset;
realio.end = realio.start + SZ_64K - 1;
status = pci_remap_iospace(&realio, cf->phys_baseaddr + CF_IO_PHYS);
if (status)
goto fail0a;