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sh_eth: place RX/TX descriptor *enum*s after their *struct*s

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Place the RX/TX descriptor bit *enum*s where they belong -- after the
corresponding RX/TX descriptor *struct*s and, while at it, switch to
declaring one *enum* entry per line...

Signed-off-by: Sergey Shtylyov <s.shtylyov@omprussia.ru>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sergey Shtylyov
2021-03-12 23:47:02 +03:00
committed by David S. Miller
parent e2dccaf194
commit 0deaeabf27
1 changed files with 46 additions and 36 deletions
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82
drivers/net/ethernet/renesas/sh_eth.h
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@ -288,27 +288,6 @@ enum EESIPR_BIT {
EESIPR_CERFIP = 0x00000001, EESIPR_CERFIP = 0x00000001,
}; };
/* Receive descriptor 0 bits */
enum RD_STS_BIT {
RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
RD_RFS1 = 0x00000001,
};
#define RDF1ST RD_RFP1
#define RDFEND RD_RFP0
#define RD_RFP (RD_RFP1|RD_RFP0)
/* Receive descriptor 1 bits */
enum RD_LEN_BIT {
RD_RFL = 0x0000ffff, /* receive frame length */
RD_RBL = 0xffff0000, /* receive buffer length */
};
/* FCFTR */ /* FCFTR */
enum FCFTR_BIT { enum FCFTR_BIT {
FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000, FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
@ -318,21 +297,6 @@ enum FCFTR_BIT {
#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0) #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0) #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
/* Transmit descriptor 0 bits */
enum TD_STS_BIT {
TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
TD_TFE = 0x08000000, TD_TWBI = 0x04000000,
};
#define TDF1ST TD_TFP1
#define TDFEND TD_TFP0
#define TD_TFP (TD_TFP1|TD_TFP0)
/* Transmit descriptor 1 bits */
enum TD_LEN_BIT {
TD_TBL = 0xffff0000, /* transmit buffer length */
};
/* RMCR */ /* RMCR */
enum RMCR_BIT { enum RMCR_BIT {
RMCR_RNC = 0x00000001, RMCR_RNC = 0x00000001,
@ -451,6 +415,24 @@ struct sh_eth_txdesc {
u32 pad0; /* padding data */ u32 pad0; /* padding data */
} __aligned(2) __packed; } __aligned(2) __packed;
/* Transmit descriptor 0 bits */
enum TD_STS_BIT {
TD_TACT = 0x80000000,
TD_TDLE = 0x40000000,
TD_TFP1 = 0x20000000,
TD_TFP0 = 0x10000000,
TD_TFE = 0x08000000,
TD_TWBI = 0x04000000,
};
#define TDF1ST TD_TFP1
#define TDFEND TD_TFP0
#define TD_TFP (TD_TFP1 | TD_TFP0)
/* Transmit descriptor 1 bits */
enum TD_LEN_BIT {
TD_TBL = 0xffff0000, /* transmit buffer length */
};
/* The sh ether Rx buffer descriptors. /* The sh ether Rx buffer descriptors.
* This structure should be 20 bytes. * This structure should be 20 bytes.
*/ */
@ -461,6 +443,34 @@ struct sh_eth_rxdesc {
u32 pad0; /* padding data */ u32 pad0; /* padding data */
} __aligned(2) __packed; } __aligned(2) __packed;
/* Receive descriptor 0 bits */
enum RD_STS_BIT {
RD_RACT = 0x80000000,
RD_RDLE = 0x40000000,
RD_RFP1 = 0x20000000,
RD_RFP0 = 0x10000000,
RD_RFE = 0x08000000,
RD_RFS10 = 0x00000200,
RD_RFS9 = 0x00000100,
RD_RFS8 = 0x00000080,
RD_RFS7 = 0x00000040,
RD_RFS6 = 0x00000020,
RD_RFS5 = 0x00000010,
RD_RFS4 = 0x00000008,
RD_RFS3 = 0x00000004,
RD_RFS2 = 0x00000002,
RD_RFS1 = 0x00000001,
};
#define RDF1ST RD_RFP1
#define RDFEND RD_RFP0
#define RD_RFP (RD_RFP1 | RD_RFP0)
/* Receive descriptor 1 bits */
enum RD_LEN_BIT {
RD_RFL = 0x0000ffff, /* receive frame length */
RD_RBL = 0xffff0000, /* receive buffer length */
};
/* This structure is used by each CPU dependency handling. */ /* This structure is used by each CPU dependency handling. */
struct sh_eth_cpu_data { struct sh_eth_cpu_data {
/* mandatory functions */ /* mandatory functions */