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dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names

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Define clock/clock-names properties of the GCC device node to be used
on APQ8084 platform.

Note: the driver uses a single pcie_pipe clock, however most probably
there are two pipe clocks, one from each of PCIe QMP PHYs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-2-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2023-01-11 08:03:51 +02:00 committed by Bjorn Andersson
parent 5f082ac76f
commit 0df0a8f2d2
1 changed files with 44 additions and 0 deletions
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44
Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
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@ -25,6 +25,30 @@ properties:
compatible:
const: qcom,gcc-apq8084
clocks:
items:
- description: XO source
- description: Sleep clock source
- description: UFS RX symbol 0 clock
- description: UFS RX symbol 1 clock
- description: UFS TX symbol 0 clock
- description: UFS TX symbol 1 clock
- description: SATA ASIC0 clock
- description: SATA RX clock
- description: PCIe PIPE clock
clock-names:
items:
- const: xo
- const: sleep_clk
- const: ufs_rx_symbol_0_clk_src
- const: ufs_rx_symbol_1_clk_src
- const: ufs_tx_symbol_0_clk_src
- const: ufs_tx_symbol_1_clk_src
- const: sata_asic0_clk
- const: sata_rx_clk
- const: pcie_pipe
required:
- compatible
@ -32,11 +56,31 @@ unevaluatedProperties: false
examples:
- |
/* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
clock-controller@fc400000 {
compatible = "qcom,gcc-apq8084";
reg = <0xfc400000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
<&ufsphy 0>,
<&ufsphy 1>,
<&ufsphy 2>,
<&ufsphy 3>,
<&sata 0>,
<&sata 1>,
<&pcie_phy>;
clock-names = "xo",
"sleep_clk",
"ufs_rx_symbol_0_clk_src",
"ufs_rx_symbol_1_clk_src",
"ufs_tx_symbol_0_clk_src",
"ufs_tx_symbol_1_clk_src",
"sata_asic0_clk",
"sata_rx_clk",
"pcie_pipe";
};
...