media: aspeed: refine hsync/vsync polarity setting logic
To prevent inaccurate detections of resolution, this commit enables clearing of hsync/vsync polarity bits based on probed sync state. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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@ -614,7 +614,7 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
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int i;
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int hsync_counter = 0;
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int vsync_counter = 0;
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u32 sts;
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u32 sts, ctrl;
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for (i = 0; i < NUM_POLARITY_CHECKS; ++i) {
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sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS);
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@ -629,30 +629,29 @@ static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
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hsync_counter++;
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}
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if (hsync_counter < 0 || vsync_counter < 0) {
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u32 ctrl = 0;
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ctrl = aspeed_video_read(video, VE_CTRL);
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if (hsync_counter < 0) {
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ctrl = VE_CTRL_HSYNC_POL;
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video->detected_timings.polarities &=
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~V4L2_DV_HSYNC_POS_POL;
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} else {
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video->detected_timings.polarities |=
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V4L2_DV_HSYNC_POS_POL;
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}
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if (vsync_counter < 0) {
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ctrl = VE_CTRL_VSYNC_POL;
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video->detected_timings.polarities &=
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~V4L2_DV_VSYNC_POS_POL;
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} else {
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video->detected_timings.polarities |=
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V4L2_DV_VSYNC_POS_POL;
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}
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if (ctrl)
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aspeed_video_update(video, VE_CTRL, 0, ctrl);
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if (hsync_counter < 0) {
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ctrl |= VE_CTRL_HSYNC_POL;
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video->detected_timings.polarities &=
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~V4L2_DV_HSYNC_POS_POL;
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} else {
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ctrl &= ~VE_CTRL_HSYNC_POL;
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video->detected_timings.polarities |=
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V4L2_DV_HSYNC_POS_POL;
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}
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if (vsync_counter < 0) {
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ctrl |= VE_CTRL_VSYNC_POL;
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video->detected_timings.polarities &=
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~V4L2_DV_VSYNC_POS_POL;
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} else {
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ctrl &= ~VE_CTRL_VSYNC_POL;
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video->detected_timings.polarities |=
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V4L2_DV_VSYNC_POS_POL;
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}
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aspeed_video_write(video, VE_CTRL, ctrl);
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}
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static bool aspeed_video_alloc_buf(struct aspeed_video *video,
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