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scsi: ufs: qcom: Use ufshcd_rmwl() where applicable

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Instead of using both ufshcd_readl() and ufshcd_writel() to read/modify/
write a register, let's make use of the existing helper.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231208065902.11006-17-manivannan.sadhasivam@linaro.org
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Manivannan Sadhasivam 2023-12-08 12:29:01 +05:30 committed by Martin K. Petersen
parent 104cd58d9a
commit 0e9f4375db
2 changed files with 7 additions and 8 deletions
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12
drivers/ufs/host/ufs-qcom.c
View File

@ -387,9 +387,8 @@ out_disable_phy:
*/ */
static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
{ {
ufshcd_writel(hba, ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2);
REG_UFS_CFG2);
/* Ensure that HW clock gating is enabled before next operations */ /* Ensure that HW clock gating is enabled before next operations */
mb(); mb();
@ -1689,11 +1688,8 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba)
platform_msi_domain_free_irqs(hba->dev); platform_msi_domain_free_irqs(hba->dev);
} else { } else {
if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
host->hw_ver.step == 0) { host->hw_ver.step == 0)
ufshcd_writel(hba, ufshcd_rmwl(hba, ESI_VEC_MASK, 0x1f00, REG_UFS_CFG3);
ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000,
REG_UFS_CFG3);
}
ufshcd_mcq_enable_esi(hba); ufshcd_mcq_enable_esi(hba);
} }

3
drivers/ufs/host/ufs-qcom.h
View File

@ -102,6 +102,9 @@ enum {
#define TMRLUT_HW_CGC_EN BIT(6) #define TMRLUT_HW_CGC_EN BIT(6)
#define OCSC_HW_CGC_EN BIT(7) #define OCSC_HW_CGC_EN BIT(7)
/* bit definitions for REG_UFS_CFG3 register */
#define ESI_VEC_MASK GENMASK(22, 12)
/* bit definitions for REG_UFS_PARAM0 */ /* bit definitions for REG_UFS_PARAM0 */
#define MAX_HS_GEAR_MASK GENMASK(6, 4) #define MAX_HS_GEAR_MASK GENMASK(6, 4)
#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) #define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x))