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net: calxedaxgmac: use raw i/o accessors in rx and tx paths

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The standard readl/writel accessors involve a spinlock and cache sync
operation on ARM platforms with an outer cache. Only DMA triggering
accesses need this, so use the raw variants instead in the critical paths.

The relaxed variants would be more appropriate, but don't exist on all
arches.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rob Herring 2012-11-05 06:22:21 +00:00 committed by David S. Miller
parent b821bd8e5a
commit 0ec6d343f7
1 changed files with 6 additions and 6 deletions
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12
drivers/net/ethernet/calxeda/xgmac.c
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@ -1203,7 +1203,7 @@ static int xgmac_poll(struct napi_struct *napi, int budget)
if (work_done < budget) { if (work_done < budget) {
napi_complete(napi); napi_complete(napi);
writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA); __raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
} }
return work_done; return work_done;
} }
@ -1348,7 +1348,7 @@ static irqreturn_t xgmac_pmt_interrupt(int irq, void *dev_id)
struct xgmac_priv *priv = netdev_priv(dev); struct xgmac_priv *priv = netdev_priv(dev);
void __iomem *ioaddr = priv->base; void __iomem *ioaddr = priv->base;
intr_status = readl(ioaddr + XGMAC_INT_STAT); intr_status = __raw_readl(ioaddr + XGMAC_INT_STAT);
if (intr_status & XGMAC_INT_STAT_PMT) { if (intr_status & XGMAC_INT_STAT_PMT) {
netdev_dbg(priv->dev, "received Magic frame\n"); netdev_dbg(priv->dev, "received Magic frame\n");
/* clear the PMT bits 5 and 6 by reading the PMT */ /* clear the PMT bits 5 and 6 by reading the PMT */
@ -1366,9 +1366,9 @@ static irqreturn_t xgmac_interrupt(int irq, void *dev_id)
struct xgmac_extra_stats *x = &priv->xstats; struct xgmac_extra_stats *x = &priv->xstats;
/* read the status register (CSR5) */ /* read the status register (CSR5) */
intr_status = readl(priv->base + XGMAC_DMA_STATUS); intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS);
intr_status &= readl(priv->base + XGMAC_DMA_INTR_ENA); intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA);
writel(intr_status, priv->base + XGMAC_DMA_STATUS); __raw_writel(intr_status, priv->base + XGMAC_DMA_STATUS);
/* It displays the DMA process states (CSR5 register) */ /* It displays the DMA process states (CSR5 register) */
/* ABNORMAL interrupts */ /* ABNORMAL interrupts */
@ -1404,7 +1404,7 @@ static irqreturn_t xgmac_interrupt(int irq, void *dev_id)
/* TX/RX NORMAL interrupts */ /* TX/RX NORMAL interrupts */
if (intr_status & (DMA_STATUS_RI | DMA_STATUS_TU)) { if (intr_status & (DMA_STATUS_RI | DMA_STATUS_TU)) {
writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA); __raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA);
napi_schedule(&priv->napi); napi_schedule(&priv->napi);
} }