dt-bindings: display/msm: add support for the display on SM8450
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8450 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/514234/ Link: https://lore.kernel.org/r/20221207012231.112059-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Dmitry Baryshkov
parent
73162e5dd4
commit
0eda3c6cb1
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8450 Display DPU
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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$ref: /schemas/display/msm/dpu-common.yaml#
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properties:
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compatible:
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const: qcom,sm8450-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display hf axi
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- description: Display sf axi
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- description: Display ahb
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- description: Display lut
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- description: Display core
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- description: Display vsync
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clock-names:
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items:
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- const: bus
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- const: nrt_bus
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- const: iface
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- const: lut
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- const: core
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- const: vsync
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sm8450.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-controller@ae01000 {
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compatible = "qcom,sm8450-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus",
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"nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-172000000{
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opp-hz = /bits/ 64 <172000000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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...
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@ -0,0 +1,343 @@
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8450 Display MDSS
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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description:
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SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
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DPU display controller, DSI and DP interfaces etc.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,sm8450-mdss
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clocks:
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items:
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- description: Display AHB
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- description: Display hf AXI
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- description: Display sf AXI
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- description: Display core
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iommus:
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maxItems: 1
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interconnects:
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maxItems: 2
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interconnect-names:
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maxItems: 2
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: qcom,sm8450-dpu
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"^dsi@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: qcom,mdss-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: qcom,dsi-phy-5nm-8450
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sm8450.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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compatible = "qcom,sm8450-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
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<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
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interconnect-names = "mdp0-mem", "mdp1-mem";
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resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "bus", "nrt_bus", "core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x2800 0x402>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sm8450-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus",
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"nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-172000000{
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opp-hz = /bits/ 64 <172000000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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phys = <&dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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};
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};
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};
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dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-160310000{
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opp-hz = /bits/ 64 <160310000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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dsi0_phy: phy@ae94400 {
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compatible = "qcom,dsi-phy-5nm-8450";
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reg = <0x0ae94400 0x200>,
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<0x0ae94600 0x280>,
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<0x0ae94900 0x260>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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vdds-supply = <&vreg_dsi_phy>;
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};
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dsi@ae96000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0x0ae96000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <5>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
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assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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phys = <&dsi1_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi1_out: endpoint {
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};
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};
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};
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};
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dsi1_phy: phy@ae96400 {
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compatible = "qcom,dsi-phy-5nm-8450";
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reg = <0x0ae96400 0x200>,
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<0x0ae96600 0x280>,
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<0x0ae96900 0x260>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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vdds-supply = <&vreg_dsi_phy>;
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};
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};
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...
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