tg3: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify tg3 driver. [bhelgaas: split bnx2x and tg3 into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -3653,17 +3653,9 @@ static int tg3_power_down_prepare(struct tg3 *tp)
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tg3_enable_register_access(tp);
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tg3_enable_register_access(tp);
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/* Restore the CLKREQ setting. */
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/* Restore the CLKREQ setting. */
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if (tg3_flag(tp, CLKREQ_BUG)) {
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if (tg3_flag(tp, CLKREQ_BUG))
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u16 lnkctl;
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pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_CLKREQ_EN);
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pci_read_config_word(tp->pdev,
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pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
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&lnkctl);
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lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
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pci_write_config_word(tp->pdev,
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pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
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lnkctl);
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}
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misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
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misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
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tw32(TG3PCI_MISC_HOST_CTRL,
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tw32(TG3PCI_MISC_HOST_CTRL,
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@ -4434,20 +4426,13 @@ relink:
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/* Prevent send BD corruption. */
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/* Prevent send BD corruption. */
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if (tg3_flag(tp, CLKREQ_BUG)) {
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if (tg3_flag(tp, CLKREQ_BUG)) {
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u16 oldlnkctl, newlnkctl;
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pci_read_config_word(tp->pdev,
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pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
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&oldlnkctl);
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if (tp->link_config.active_speed == SPEED_100 ||
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if (tp->link_config.active_speed == SPEED_100 ||
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tp->link_config.active_speed == SPEED_10)
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tp->link_config.active_speed == SPEED_10)
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newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
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pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_CLKREQ_EN);
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else
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else
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newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
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pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
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if (newlnkctl != oldlnkctl)
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PCI_EXP_LNKCTL_CLKREQ_EN);
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pci_write_config_word(tp->pdev,
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pci_pcie_cap(tp->pdev) +
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PCI_EXP_LNKCTL, newlnkctl);
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}
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}
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if (current_link_up != netif_carrier_ok(tp->dev)) {
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if (current_link_up != netif_carrier_ok(tp->dev)) {
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@ -8054,7 +8039,7 @@ static int tg3_chip_reset(struct tg3 *tp)
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udelay(120);
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udelay(120);
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if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
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if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
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u16 val16;
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u16 val16;
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if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
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if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
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@ -8071,24 +8056,17 @@ static int tg3_chip_reset(struct tg3 *tp)
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}
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}
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/* Clear the "no snoop" and "relaxed ordering" bits. */
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/* Clear the "no snoop" and "relaxed ordering" bits. */
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pci_read_config_word(tp->pdev,
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val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
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pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
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&val16);
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val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
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PCI_EXP_DEVCTL_NOSNOOP_EN);
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/*
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/*
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* Older PCIe devices only support the 128 byte
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* Older PCIe devices only support the 128 byte
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* MPS setting. Enforce the restriction.
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* MPS setting. Enforce the restriction.
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*/
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*/
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if (!tg3_flag(tp, CPMU_PRESENT))
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if (!tg3_flag(tp, CPMU_PRESENT))
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val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
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val16 |= PCI_EXP_DEVCTL_PAYLOAD;
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pci_write_config_word(tp->pdev,
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pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
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pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
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val16);
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/* Clear error status */
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/* Clear error status */
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pci_write_config_word(tp->pdev,
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pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
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pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
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PCI_EXP_DEVSTA_CED |
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PCI_EXP_DEVSTA_CED |
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PCI_EXP_DEVSTA_NFED |
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PCI_EXP_DEVSTA_NFED |
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PCI_EXP_DEVSTA_FED |
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PCI_EXP_DEVSTA_FED |
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@ -14565,9 +14543,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tg3_flag_set(tp, PCI_EXPRESS);
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tg3_flag_set(tp, PCI_EXPRESS);
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pci_read_config_word(tp->pdev,
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pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
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pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
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&lnkctl);
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if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
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if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
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if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
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ASIC_REV_5906) {
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ASIC_REV_5906) {
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