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clk: mediatek: Switch to mtk_clk_simple_probe() where possible

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mtk_clk_simple_probe() is a function that registers mtk gate clocks
and, if reset data is present, a reset controller and across all of
the MTK clock drivers, such a function is duplicated many times:
switch to the common mtk_clk_simple_probe() function for all of the
clock drivers that are registering as platform drivers.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2023-01-20 10:20:41 +01:00 committed by Stephen Boyd
parent 4c02c9af3c
commit 0f69a423c4
14 changed files with 267 additions and 564 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/clk/mediatek/clk-mt2701-aud.c
View File

@ -76,6 +76,7 @@ static const struct mtk_gate_regs audio3_cg_regs = {
};
static const struct mtk_gate audio_clks[] = {
GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
/* AUDIO0 */
GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
@ -138,29 +139,27 @@ static const struct mtk_gate audio_clks[] = {
GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
};
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
};
static const struct of_device_id of_match_clk_mt2701_aud[] = {
{ .compatible = "mediatek,mt2701-audsys", },
{}
{ .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
{ /* sentinel */ }
};
static int clk_mt2701_aud_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
mtk_clk_register_gates(&pdev->dev, node, audio_clks,
ARRAY_SIZE(audio_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
r = mtk_clk_simple_probe(pdev);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
goto err_clk_provider;
return r;
}
r = devm_of_platform_populate(&pdev->dev);
@ -170,13 +169,19 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev)
return 0;
err_plat_populate:
of_clk_del_provider(node);
err_clk_provider:
mtk_clk_simple_remove(pdev);
return r;
}
static int clk_mt2701_aud_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
return mtk_clk_simple_remove(pdev);
}
static struct platform_driver clk_mt2701_aud_drv = {
.probe = clk_mt2701_aud_probe,
.remove = clk_mt2701_aud_remove,
.driver = {
.name = "clk-mt2701-aud",
.of_match_table = of_match_clk_mt2701_aud,

36
drivers/clk/mediatek/clk-mt2701-eth.c
View File

@ -26,6 +26,7 @@ static const struct mtk_gate_regs eth_cg_regs = {
}
static const struct mtk_gate eth_clks[] = {
GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
@ -44,35 +45,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct of_device_id of_match_clk_mt2701_eth[] = {
{ .compatible = "mediatek,mt2701-ethsys", },
{}
static const struct mtk_clk_desc eth_desc = {
.clks = eth_clks,
.num_clks = ARRAY_SIZE(eth_clks),
.rst_desc = &clk_rst_desc,
};
static int clk_mt2701_eth_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
mtk_clk_register_gates(&pdev->dev, node, eth_clks,
ARRAY_SIZE(eth_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static const struct of_device_id of_match_clk_mt2701_eth[] = {
{ .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt2701_eth_drv = {
.probe = clk_mt2701_eth_probe,
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-eth",
.of_match_table = of_match_clk_mt2701_eth,

58
drivers/clk/mediatek/clk-mt2701-g3d.c
View File

@ -32,6 +32,7 @@ static const struct mtk_gate_regs g3d_cg_regs = {
};
static const struct mtk_gate g3d_clks[] = {
GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
};
@ -43,57 +44,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static const struct of_device_id of_match_clk_mt2701_g3d[] = {
{
.compatible = "mediatek,mt2701-g3dsys",
.data = clk_mt2701_g3dsys_init,
}, {
/* sentinel */
}
static const struct mtk_clk_desc g3d_desc = {
.clks = g3d_clks,
.num_clks = ARRAY_SIZE(g3d_clks),
.rst_desc = &clk_rst_desc,
};
static int clk_mt2701_g3d_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static const struct of_device_id of_match_clk_mt2701_g3d[] = {
{ .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt2701_g3d_drv = {
.probe = clk_mt2701_g3d_probe,
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-g3d",
.of_match_table = of_match_clk_mt2701_g3d,

38
drivers/clk/mediatek/clk-mt2701-hif.c
View File

@ -26,6 +26,7 @@ static const struct mtk_gate_regs hif_cg_regs = {
}
static const struct mtk_gate hif_clks[] = {
GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
@ -41,37 +42,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static const struct of_device_id of_match_clk_mt2701_hif[] = {
{ .compatible = "mediatek,mt2701-hifsys", },
{}
static const struct mtk_clk_desc hif_desc = {
.clks = hif_clks,
.num_clks = ARRAY_SIZE(hif_clks),
.rst_desc = &clk_rst_desc,
};
static int clk_mt2701_hif_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
mtk_clk_register_gates(&pdev->dev, node, hif_clks,
ARRAY_SIZE(hif_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return 0;
}
static const struct of_device_id of_match_clk_mt2701_hif[] = {
{ .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt2701_hif_drv = {
.probe = clk_mt2701_hif_probe,
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2701-hif",
.of_match_table = of_match_clk_mt2701_hif,

83
drivers/clk/mediatek/clk-mt2712.c
View File

@ -1363,50 +1363,6 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
return r;
}
static int clk_mt2712_infra_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
return r;
}
static int clk_mt2712_peri_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
return r;
}
static int clk_mt2712_mcu_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
@ -1444,12 +1400,6 @@ static const struct of_device_id of_match_clk_mt2712[] = {
}, {
.compatible = "mediatek,mt2712-topckgen",
.data = clk_mt2712_top_probe,
}, {
.compatible = "mediatek,mt2712-infracfg",
.data = clk_mt2712_infra_probe,
}, {
.compatible = "mediatek,mt2712-pericfg",
.data = clk_mt2712_peri_probe,
}, {
.compatible = "mediatek,mt2712-mcucfg",
.data = clk_mt2712_mcu_probe,
@ -1476,6 +1426,33 @@ static int clk_mt2712_probe(struct platform_device *pdev)
return r;
}
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.rst_desc = &clk_rst_desc[0],
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_clks,
.num_clks = ARRAY_SIZE(peri_clks),
.rst_desc = &clk_rst_desc[1],
};
static const struct of_device_id of_match_clk_mt2712_simple[] = {
{ .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
{ .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
{ /* sentinel */ }
};
static struct platform_driver clk_mt2712_simple_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt2712-simple",
.of_match_table = of_match_clk_mt2712_simple,
},
};
static struct platform_driver clk_mt2712_drv = {
.probe = clk_mt2712_probe,
.driver = {
@ -1486,7 +1463,11 @@ static struct platform_driver clk_mt2712_drv = {
static int __init clk_mt2712_init(void)
{
return platform_driver_register(&clk_mt2712_drv);
int ret = platform_driver_register(&clk_mt2712_drv);
if (ret)
return ret;
return platform_driver_register(&clk_mt2712_simple_drv);
}
arch_initcall(clk_mt2712_init);

42
drivers/clk/mediatek/clk-mt6779.c
View File

@ -880,6 +880,7 @@ static const struct mtk_gate_regs infra3_cg_regs = {
&mtk_clk_gate_ops_setclr)
static const struct mtk_gate infra_clks[] = {
GATE_DUMMY(CLK_DUMMY, "ifa_dummy"),
/* INFRA0 */
GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
"axi_sel", 0),
@ -1259,19 +1260,6 @@ static int clk_mt6779_top_probe(struct platform_device *pdev)
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int clk_mt6779_infra_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt6779[] = {
{
.compatible = "mediatek,mt6779-apmixed",
@ -1279,9 +1267,6 @@ static const struct of_device_id of_match_clk_mt6779[] = {
}, {
.compatible = "mediatek,mt6779-topckgen",
.data = clk_mt6779_top_probe,
}, {
.compatible = "mediatek,mt6779-infracfg_ao",
.data = clk_mt6779_infra_probe,
}, {
/* sentinel */
}
@ -1305,6 +1290,25 @@ static int clk_mt6779_probe(struct platform_device *pdev)
return r;
}
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
};
static const struct of_device_id of_match_clk_mt6779_infra[] = {
{ .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt6779_infra_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt6779-infra",
.of_match_table = of_match_clk_mt6779_infra,
},
};
static struct platform_driver clk_mt6779_drv = {
.probe = clk_mt6779_probe,
.driver = {
@ -1315,7 +1319,11 @@ static struct platform_driver clk_mt6779_drv = {
static int __init clk_mt6779_init(void)
{
return platform_driver_register(&clk_mt6779_drv);
int ret = platform_driver_register(&clk_mt6779_drv);
if (ret)
return ret;
return platform_driver_register(&clk_mt6779_infra_drv);
}
arch_initcall(clk_mt6779_init);

54
drivers/clk/mediatek/clk-mt7622-aud.c
View File

@ -130,24 +130,22 @@ static const struct mtk_gate audio_clks[] = {
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
};
static int clk_mt7622_audiosys_init(struct platform_device *pdev)
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
};
static int clk_mt7622_aud_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, audio_clks,
ARRAY_SIZE(audio_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
r = mtk_clk_simple_probe(pdev);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
goto err_clk_provider;
return r;
}
r = devm_of_platform_populate(&pdev->dev);
@ -157,40 +155,24 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
return 0;
err_plat_populate:
of_clk_del_provider(node);
err_clk_provider:
mtk_clk_simple_remove(pdev);
return r;
}
static int clk_mt7622_aud_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
return mtk_clk_simple_remove(pdev);
}
static const struct of_device_id of_match_clk_mt7622_aud[] = {
{
.compatible = "mediatek,mt7622-audsys",
.data = clk_mt7622_audiosys_init,
}, {
/* sentinel */
}
{ .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
{ /* sentinel */ }
};
static int clk_mt7622_aud_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static struct platform_driver clk_mt7622_aud_drv = {
.probe = clk_mt7622_aud_probe,
.remove = clk_mt7622_aud_remove,
.driver = {
.name = "clk-mt7622-aud",
.of_match_table = of_match_clk_mt7622_aud,

84
drivers/clk/mediatek/clk-mt7622-eth.c
View File

@ -73,80 +73,26 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7622_ethsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, eth_clks,
ARRAY_SIZE(eth_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
ARRAY_SIZE(sgmii_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static const struct of_device_id of_match_clk_mt7622_eth[] = {
{
.compatible = "mediatek,mt7622-ethsys",
.data = clk_mt7622_ethsys_init,
}, {
.compatible = "mediatek,mt7622-sgmiisys",
.data = clk_mt7622_sgmiisys_init,
}, {
/* sentinel */
}
static const struct mtk_clk_desc eth_desc = {
.clks = eth_clks,
.num_clks = ARRAY_SIZE(eth_clks),
.rst_desc = &clk_rst_desc,
};
static int clk_mt7622_eth_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
static const struct mtk_clk_desc sgmii_desc = {
.clks = sgmii_clks,
.num_clks = ARRAY_SIZE(sgmii_clks),
};
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static const struct of_device_id of_match_clk_mt7622_eth[] = {
{ .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt7622_eth_drv = {
.probe = clk_mt7622_eth_probe,
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-eth",
.of_match_table = of_match_clk_mt7622_eth,

87
drivers/clk/mediatek/clk-mt7622-hif.c
View File

@ -84,82 +84,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
ARRAY_SIZE(ssusb_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static int clk_mt7622_pciesys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
ARRAY_SIZE(pcie_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static const struct of_device_id of_match_clk_mt7622_hif[] = {
{
.compatible = "mediatek,mt7622-pciesys",
.data = clk_mt7622_pciesys_init,
}, {
.compatible = "mediatek,mt7622-ssusbsys",
.data = clk_mt7622_ssusbsys_init,
}, {
/* sentinel */
}
static const struct mtk_clk_desc ssusb_desc = {
.clks = ssusb_clks,
.num_clks = ARRAY_SIZE(ssusb_clks),
.rst_desc = &clk_rst_desc,
};
static int clk_mt7622_hif_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
static const struct mtk_clk_desc pcie_desc = {
.clks = pcie_clks,
.num_clks = ARRAY_SIZE(pcie_clks),
.rst_desc = &clk_rst_desc,
};
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static const struct of_device_id of_match_clk_mt7622_hif[] = {
{ .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
{ .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt7622_hif_drv = {
.probe = clk_mt7622_hif_probe,
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7622-hif",
.of_match_table = of_match_clk_mt7622_hif,

87
drivers/clk/mediatek/clk-mt7629-hif.c
View File

@ -79,82 +79,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = {
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
};
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
ARRAY_SIZE(ssusb_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static int clk_mt7629_pciesys_init(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
ARRAY_SIZE(pcie_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static const struct of_device_id of_match_clk_mt7629_hif[] = {
{
.compatible = "mediatek,mt7629-pciesys",
.data = clk_mt7629_pciesys_init,
}, {
.compatible = "mediatek,mt7629-ssusbsys",
.data = clk_mt7629_ssusbsys_init,
}, {
/* sentinel */
}
static const struct mtk_clk_desc ssusb_desc = {
.clks = ssusb_clks,
.num_clks = ARRAY_SIZE(ssusb_clks),
.rst_desc = &clk_rst_desc,
};
static int clk_mt7629_hif_probe(struct platform_device *pdev)
{
int (*clk_init)(struct platform_device *);
int r;
static const struct mtk_clk_desc pcie_desc = {
.clks = pcie_clks,
.num_clks = ARRAY_SIZE(pcie_clks),
.rst_desc = &clk_rst_desc,
};
clk_init = of_device_get_match_data(&pdev->dev);
if (!clk_init)
return -EINVAL;
r = clk_init(pdev);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return r;
}
static const struct of_device_id of_match_clk_mt7629_hif[] = {
{ .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
{ .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt7629_hif_drv = {
.probe = clk_mt7629_hif_probe,
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt7629-hif",
.of_match_table = of_match_clk_mt7629_hif,

27
drivers/clk/mediatek/clk-mt8183-audio.c
View File

@ -67,35 +67,40 @@ static const struct mtk_gate audio_clks[] = {
20),
};
static const struct mtk_clk_desc audio_desc = {
.clks = audio_clks,
.num_clks = ARRAY_SIZE(audio_clks),
};
static int clk_mt8183_audio_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, audio_clks,
ARRAY_SIZE(audio_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
r = mtk_clk_simple_probe(pdev);
if (r)
return r;
r = devm_of_platform_populate(&pdev->dev);
if (r)
of_clk_del_provider(node);
mtk_clk_simple_remove(pdev);
return r;
}
static int clk_mt8183_audio_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
return mtk_clk_simple_remove(pdev);
}
static const struct of_device_id of_match_clk_mt8183_audio[] = {
{ .compatible = "mediatek,mt8183-audiosys", },
{}
{ .compatible = "mediatek,mt8183-audiosys", .data = &audio_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt8183_audio_drv = {
.probe = clk_mt8183_audio_probe,
.remove = clk_mt8183_audio_remove,
.driver = {
.name = "clk-mt8183-audio",
.of_match_table = of_match_clk_mt8183_audio,

75
drivers/clk/mediatek/clk-mt8183.c
View File

@ -1190,43 +1190,6 @@ static int clk_mt8183_top_probe(struct platform_device *pdev)
top_clk_data);
}
static int clk_mt8183_infra_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
dev_err(&pdev->dev,
"%s(): could not register clock provider: %d\n",
__func__, r);
return r;
}
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
return r;
}
static int clk_mt8183_peri_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int clk_mt8183_mcu_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
@ -1253,12 +1216,6 @@ static const struct of_device_id of_match_clk_mt8183[] = {
}, {
.compatible = "mediatek,mt8183-topckgen",
.data = clk_mt8183_top_probe,
}, {
.compatible = "mediatek,mt8183-infracfg",
.data = clk_mt8183_infra_probe,
}, {
.compatible = "mediatek,mt8183-pericfg",
.data = clk_mt8183_peri_probe,
}, {
.compatible = "mediatek,mt8183-mcucfg",
.data = clk_mt8183_mcu_probe,
@ -1285,6 +1242,32 @@ static int clk_mt8183_probe(struct platform_device *pdev)
return r;
}
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.rst_desc = &clk_rst_desc,
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_clks,
.num_clks = ARRAY_SIZE(peri_clks),
};
static const struct of_device_id of_match_clk_mt8183_simple[] = {
{ .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc },
{ .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, },
{ /* sentinel */ }
};
static struct platform_driver clk_mt8183_simple_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8183-simple",
.of_match_table = of_match_clk_mt8183_simple,
},
};
static struct platform_driver clk_mt8183_drv = {
.probe = clk_mt8183_probe,
.driver = {
@ -1295,7 +1278,11 @@ static struct platform_driver clk_mt8183_drv = {
static int __init clk_mt8183_init(void)
{
return platform_driver_register(&clk_mt8183_drv);
int ret = platform_driver_register(&clk_mt8183_drv);
if (ret)
return ret;
return platform_driver_register(&clk_mt8183_simple_drv);
}
arch_initcall(clk_mt8183_init);

31
drivers/clk/mediatek/clk-mt8192-aud.c
View File

@ -77,39 +77,40 @@ static const struct mtk_gate aud_clks[] = {
GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4),
};
static const struct mtk_clk_desc aud_desc = {
.clks = aud_clks,
.num_clks = ARRAY_SIZE(aud_clks),
};
static int clk_mt8192_aud_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_gates(&pdev->dev, node, aud_clks,
ARRAY_SIZE(aud_clks), clk_data);
if (r)
return r;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
r = mtk_clk_simple_probe(pdev);
if (r)
return r;
r = devm_of_platform_populate(&pdev->dev);
if (r)
of_clk_del_provider(node);
mtk_clk_simple_remove(pdev);
return r;
}
static int clk_mt8192_aud_remove(struct platform_device *pdev)
{
of_platform_depopulate(&pdev->dev);
return mtk_clk_simple_remove(pdev);
}
static const struct of_device_id of_match_clk_mt8192_aud[] = {
{ .compatible = "mediatek,mt8192-audsys", },
{}
{ .compatible = "mediatek,mt8192-audsys", .data = &aud_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt8192_aud_drv = {
.probe = clk_mt8192_aud_probe,
.remove = clk_mt8192_aud_remove,
.driver = {
.name = "clk-mt8192-aud",
.of_match_table = of_match_clk_mt8192_aud,

98
drivers/clk/mediatek/clk-mt8192.c
View File

@ -1164,66 +1164,6 @@ unregister_fixed_clks:
return r;
}
static int clk_mt8192_infra_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_gates(&pdev->dev, node, infra_clks,
ARRAY_SIZE(infra_clks), clk_data);
if (r)
goto free_clk_data;
r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
if (r)
goto unregister_gates;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_gates;
return r;
unregister_gates:
mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
}
static int clk_mt8192_peri_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_gates(&pdev->dev, node, peri_clks,
ARRAY_SIZE(peri_clks), clk_data);
if (r)
goto free_clk_data;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_gates;
return r;
unregister_gates:
mtk_clk_unregister_gates(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
free_clk_data:
mtk_free_clk_data(clk_data);
return r;
}
static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
@ -1260,12 +1200,6 @@ static const struct of_device_id of_match_clk_mt8192[] = {
}, {
.compatible = "mediatek,mt8192-topckgen",
.data = clk_mt8192_top_probe,
}, {
.compatible = "mediatek,mt8192-infracfg",
.data = clk_mt8192_infra_probe,
}, {
.compatible = "mediatek,mt8192-pericfg",
.data = clk_mt8192_peri_probe,
}, {
/* sentinel */
}
@ -1287,6 +1221,32 @@ static int clk_mt8192_probe(struct platform_device *pdev)
return r;
}
static const struct mtk_clk_desc infra_desc = {
.clks = infra_clks,
.num_clks = ARRAY_SIZE(infra_clks),
.rst_desc = &clk_rst_desc,
};
static const struct mtk_clk_desc peri_desc = {
.clks = peri_clks,
.num_clks = ARRAY_SIZE(peri_clks),
};
static const struct of_device_id of_match_clk_mt8192_simple[] = {
{ .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc },
{ .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc },
{ /* sentinel */ }
};
static struct platform_driver clk_mt8192_simple_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8192-simple",
.of_match_table = of_match_clk_mt8192_simple,
},
};
static struct platform_driver clk_mt8192_drv = {
.probe = clk_mt8192_probe,
.driver = {
@ -1297,7 +1257,11 @@ static struct platform_driver clk_mt8192_drv = {
static int __init clk_mt8192_init(void)
{
return platform_driver_register(&clk_mt8192_drv);
int ret = platform_driver_register(&clk_mt8192_drv);
if (ret)
return ret;
return platform_driver_register(&clk_mt8192_simple_drv);
}
arch_initcall(clk_mt8192_init);