powerpc/64: Fix msr_check_and_set/clear MSR[EE] race
irq soft-masking means that when Linux irqs are disabled, the MSR[EE] value can change from 1 to 0 asynchronously: if a masked interrupt of the PACA_IRQ_MUST_HARD_MASK variety fires while irqs are disabled, the masked handler will return with MSR[EE]=0. This means a sequence like mtmsr(mfmsr() | MSR_FP) is racy if it can be called with local irqs disabled, unless a hard_irq_disable has been done. Reported-by: Sachin Sant <sachinp@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221004051157.308999-2-npiggin@gmail.com
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@ -471,6 +471,30 @@ static inline void irq_soft_mask_regs_set_state(struct pt_regs *regs, unsigned l
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}
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#endif /* CONFIG_PPC64 */
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static inline unsigned long mtmsr_isync_irqsafe(unsigned long msr)
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{
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#ifdef CONFIG_PPC64
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if (arch_irqs_disabled()) {
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/*
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* With soft-masking, MSR[EE] can change from 1 to 0
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* asynchronously when irqs are disabled, and we don't want to
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* set MSR[EE] back to 1 here if that has happened. A race-free
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* way to do this is ensure EE is already 0. Another way it
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* could be done is with a RESTART_TABLE handler, but that's
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* probably overkill here.
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*/
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msr &= ~MSR_EE;
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mtmsr_isync(msr);
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irq_soft_mask_set(IRQS_ALL_DISABLED);
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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} else
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#endif
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mtmsr_isync(msr);
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return msr;
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}
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#define ARCH_IRQ_INIT_FLAGS IRQ_NOREQUEST
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#endif /* __ASSEMBLY__ */
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@ -127,7 +127,7 @@ unsigned long notrace msr_check_and_set(unsigned long bits)
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newmsr |= MSR_VSX;
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if (oldmsr != newmsr)
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mtmsr_isync(newmsr);
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newmsr = mtmsr_isync_irqsafe(newmsr);
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return newmsr;
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}
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@ -145,7 +145,7 @@ void notrace __msr_check_and_clear(unsigned long bits)
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newmsr &= ~MSR_VSX;
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if (oldmsr != newmsr)
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mtmsr_isync(newmsr);
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mtmsr_isync_irqsafe(newmsr);
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}
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EXPORT_SYMBOL(__msr_check_and_clear);
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