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drm/nouveau/fifo: use runlist engine info to lookup engine classes

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2022-06-01 20:47:26 +10:00
parent 468fae7bb0
commit 0fc72ee9d8
22 changed files with 35 additions and 146 deletions
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1
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
View File

@ -22,7 +22,6 @@ struct nvkm_chan {
union { int id; int chid; }; /*FIXME: remove later */
struct nvkm_fifo *fifo;
u32 engm;
struct nvkm_object object;
struct list_head head;

46
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
View File

@ -216,50 +216,6 @@ nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size,
return 0;
}
static int
nvkm_fifo_chan_child_get(struct nvkm_object *object, int index,
struct nvkm_oclass *oclass)
{
struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);
struct nvkm_fifo *fifo = chan->fifo;
struct nvkm_engine *engine;
u32 engm = chan->engm;
int engi, ret, c;
for (; c = 0, engi = __ffs(engm), engm; engm &= ~(1ULL << engi)) {
if (!(engine = fifo->func->id_engine(fifo, engi)))
continue;
oclass->engine = engine;
oclass->base.oclass = 0;
if (engine->func->fifo.sclass) {
ret = engine->func->fifo.sclass(oclass, index);
if (oclass->base.oclass) {
if (!oclass->base.ctor)
oclass->base.ctor = nvkm_object_new;
oclass->ctor = nvkm_fifo_chan_child_new;
return 0;
}
index -= ret;
continue;
}
while (engine->func->sclass[c].oclass) {
if (c++ == index) {
oclass->base = engine->func->sclass[index];
if (!oclass->base.ctor)
oclass->base.ctor = nvkm_object_new;
oclass->ctor = nvkm_fifo_chan_child_new;
return 0;
}
}
index -= c;
}
return -EINVAL;
}
static int
nvkm_fifo_chan_uevent(struct nvkm_object *object, void *argv, u32 argc, struct nvkm_uevent *uevent)
{
@ -355,7 +311,6 @@ nvkm_fifo_chan_func = {
.init = nvkm_fifo_chan_init,
.fini = nvkm_fifo_chan_fini,
.map = nvkm_fifo_chan_map,
.sclass = nvkm_fifo_chan_child_get,
.uevent = nvkm_fifo_chan_uevent,
};
@ -407,7 +362,6 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *fn,
nvkm_object_ctor(&nvkm_fifo_chan_func, oclass, &chan->object);
chan->fifo = fifo;
chan->engm = engm;
INIT_LIST_HEAD(&chan->head);
/* Join channel group.

47
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
View File

@ -51,52 +51,6 @@ g84_fifo_uevent_init(struct nvkm_fifo *fifo)
nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
}
struct nvkm_engine *
g84_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
{
struct nvkm_device *device = fifo->engine.subdev.device;
struct nvkm_engine *engine;
enum nvkm_subdev_type type;
switch (engi) {
case G84_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break;
case G84_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break;
case G84_FIFO_ENGN_MPEG :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPPP, 0)))
return engine;
type = NVKM_ENGINE_MPEG;
break;
case G84_FIFO_ENGN_ME :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_CE, 0)))
return engine;
type = NVKM_ENGINE_ME;
break;
case G84_FIFO_ENGN_VP :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPDEC, 0)))
return engine;
type = NVKM_ENGINE_VP;
break;
case G84_FIFO_ENGN_CIPHER:
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_VIC, 0)))
return engine;
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_SEC, 0)))
return engine;
type = NVKM_ENGINE_CIPHER;
break;
case G84_FIFO_ENGN_BSP :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSVLD, 0)))
return engine;
type = NVKM_ENGINE_BSP;
break;
case G84_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break;
default:
WARN_ON(1);
return NULL;
}
return nvkm_device_engine(fifo->engine.subdev.device, type, 0);
}
int
g84_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
@ -149,7 +103,6 @@ g84_fifo = {
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = g84_fifo_engine_id,
.id_engine = g84_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.uevent_init = g84_fifo_uevent_init,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.c
View File

@ -57,7 +57,6 @@ g98_fifo = {
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = g84_fifo_engine_id,
.id_engine = g84_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.uevent_init = g84_fifo_uevent_init,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@ -741,7 +741,6 @@ gf100_fifo = {
.intr = gf100_fifo_intr,
.mmu_fault = &gf100_fifo_mmu_fault,
.engine_id = gf100_fifo_engine_id,
.id_engine = gf100_fifo_id_engine,
.uevent_init = gf100_fifo_uevent_init,
.uevent_fini = gf100_fifo_uevent_fini,
.runl = &gf100_runl,

10
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@ -303,15 +303,6 @@ gk104_fifo_pbdma = {
.init = gk104_fifo_pbdma_init,
};
struct nvkm_engine *
gk104_fifo_id_engine(struct nvkm_fifo *base, int engi)
{
if (engi == GK104_FIFO_ENGN_SW)
return nvkm_device_engine(base->engine.subdev.device, NVKM_ENGINE_SW, 0);
return gk104_fifo(base)->engine[engi].engine;
}
int
gk104_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
@ -1185,7 +1176,6 @@ gk104_fifo = {
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c
View File

@ -93,7 +93,6 @@ gk110_fifo = {
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
View File

@ -72,7 +72,6 @@ gk208_fifo = {
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
View File

@ -43,7 +43,6 @@ gk20a_fifo = {
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
View File

@ -133,7 +133,6 @@ gm107_fifo = {
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
View File

@ -63,7 +63,6 @@ gm200_fifo = {
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
View File

@ -105,7 +105,6 @@ gp100_fifo = {
.fault.hubclient = gk104_fifo_fault_hubclient,
.fault.gpcclient = gk104_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
View File

@ -332,7 +332,6 @@ gv100_fifo = {
.fault.hubclient = gv100_fifo_fault_hubclient,
.fault.gpcclient = gv100_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

19
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
View File

@ -182,24 +182,6 @@ const struct nvkm_runl_func
nv04_runl = {
};
struct nvkm_engine *
nv04_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
{
enum nvkm_subdev_type type;
switch (engi) {
case NV04_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break;
case NV04_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break;
case NV04_FIFO_ENGN_MPEG: type = NVKM_ENGINE_MPEG; break;
case NV04_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break;
default:
WARN_ON(1);
return NULL;
}
return nvkm_device_engine(fifo->engine.subdev.device, type, 0);
}
int
nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
@ -500,7 +482,6 @@ nv04_fifo = {
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.runl = &nv04_runl,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
View File

@ -61,7 +61,6 @@ nv10_fifo = {
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.runl = &nv04_runl,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
View File

@ -93,7 +93,6 @@ nv17_fifo = {
.init = nv17_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.runl = &nv04_runl,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View File

@ -133,7 +133,6 @@ nv40_fifo = {
.init = nv40_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.runl = &nv04_runl,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
View File

@ -168,7 +168,6 @@ nv50_fifo = {
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.runl = &nv50_runl,

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
View File

@ -19,7 +19,6 @@ void nv50_fifo_init(struct nvkm_fifo *);
void nv50_fifo_runlist_update(struct nv50_fifo *);
int g84_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *g84_fifo_id_engine(struct nvkm_fifo *, int);
void g84_fifo_uevent_init(struct nvkm_fifo *);
void g84_fifo_uevent_fini(struct nvkm_fifo *);
#endif

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
View File

@ -44,7 +44,6 @@ struct nvkm_fifo_func {
} fault;
int (*engine_id)(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *(*id_engine)(struct nvkm_fifo *, int engi);
void (*pause)(struct nvkm_fifo *, unsigned long *);
void (*start)(struct nvkm_fifo *, unsigned long *);
void (*uevent_init)(struct nvkm_fifo *);
@ -98,7 +97,6 @@ int nv04_fifo_runl_ctor(struct nvkm_fifo *);
void nv04_fifo_init(struct nvkm_fifo *);
void nv04_fifo_intr(struct nvkm_fifo *);
int nv04_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *nv04_fifo_id_engine(struct nvkm_fifo *, int);
void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
extern const struct nvkm_runl_func nv04_runl;
@ -127,7 +125,6 @@ extern const struct nvkm_fifo_func_mmu_fault gk104_fifo_mmu_fault;
void gk104_fifo_fault(struct nvkm_fifo *, struct nvkm_fault_data *);
void gk104_fifo_recover_chan(struct nvkm_fifo *, int);
int gk104_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *gk104_fifo_id_engine(struct nvkm_fifo *, int);
extern const struct nvkm_runq_func gk104_runq;
extern const struct nvkm_engn_func gk104_engn;
extern const struct nvkm_engn_func gk104_engn_ce;

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
View File

@ -459,7 +459,6 @@ tu102_fifo = {
.fault.hubclient = gv100_fifo_fault_hubclient,
.fault.gpcclient = gv100_fifo_fault_gpcclient,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = tu102_fifo_recover_chan,

40
drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.c
View File

@ -22,6 +22,7 @@
#define nvkm_uchan(p) container_of((p), struct nvkm_uchan, object)
#include "cgrp.h"
#include "chan.h"
#include "runl.h"
#include <core/oproxy.h>
@ -89,14 +90,43 @@ static int
nvkm_uchan_sclass(struct nvkm_object *object, int index, struct nvkm_oclass *oclass)
{
struct nvkm_chan *chan = nvkm_uchan(object)->chan;
struct nvkm_engn *engn;
int ret;
ret = chan->object.func->sclass(&chan->object, index, oclass);
if (ret)
return ret;
nvkm_runl_foreach_engn(engn, chan->cgrp->runl) {
struct nvkm_engine *engine = engn->engine;
int c = 0;
oclass->ctor = nvkm_uchan_object_new;
return 0;
oclass->engine = engine;
oclass->base.oclass = 0;
if (engine->func->fifo.sclass) {
ret = engine->func->fifo.sclass(oclass, index);
if (oclass->base.oclass) {
if (!oclass->base.ctor)
oclass->base.ctor = nvkm_object_new;
oclass->ctor = nvkm_uchan_object_new;
return 0;
}
index -= ret;
continue;
}
while (engine->func->sclass[c].oclass) {
if (c++ == index) {
oclass->base = engine->func->sclass[index];
if (!oclass->base.ctor)
oclass->base.ctor = nvkm_object_new;
oclass->ctor = nvkm_uchan_object_new;
return 0;
}
}
index -= c;
}
return -EINVAL;
}
static int