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drm/i915: move wm_disp funcs to display.funcs

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Move display watermark functions under drm_i915_private display
sub-struct.

Rename struct drm_i915_wm_disp_funcs to intel_wm_funcs while at it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/29d07c82ef7d33a59fc9c8e25ae2d2f900677a4c.1661346845.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2022-08-24 16:15:31 +03:00
parent 5a04eb5be8
commit 103472c13f
4 changed files with 59 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -165,16 +165,16 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
*/
void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
if (dev_priv->wm_disp->update_wm)
dev_priv->wm_disp->update_wm(dev_priv);
if (dev_priv->display.funcs.wm->update_wm)
dev_priv->display.funcs.wm->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (dev_priv->wm_disp->compute_pipe_wm)
return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
if (dev_priv->display.funcs.wm->compute_pipe_wm)
return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc);
return 0;
}
@ -182,20 +182,20 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (!dev_priv->wm_disp->compute_intermediate_wm)
if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
return 0;
if (drm_WARN_ON(&dev_priv->drm,
!dev_priv->wm_disp->compute_pipe_wm))
!dev_priv->display.funcs.wm->compute_pipe_wm))
return 0;
return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc);
}
static bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (dev_priv->wm_disp->initial_watermarks) {
dev_priv->wm_disp->initial_watermarks(state, crtc);
if (dev_priv->display.funcs.wm->initial_watermarks) {
dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
return true;
}
return false;
@ -205,23 +205,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (dev_priv->wm_disp->atomic_update_watermarks)
dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
if (dev_priv->display.funcs.wm->atomic_update_watermarks)
dev_priv->display.funcs.wm->atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (dev_priv->wm_disp->optimize_watermarks)
dev_priv->wm_disp->optimize_watermarks(state, crtc);
if (dev_priv->display.funcs.wm->optimize_watermarks)
dev_priv->display.funcs.wm->optimize_watermarks(state, crtc);
}
static int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (dev_priv->wm_disp->compute_global_watermarks)
return dev_priv->wm_disp->compute_global_watermarks(state);
if (dev_priv->display.funcs.wm->compute_global_watermarks)
return dev_priv->display.funcs.wm->compute_global_watermarks(state);
return 0;
}
@ -2401,7 +2401,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->wm_disp->initial_watermarks)
if (!dev_priv->display.funcs.wm->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@ -8455,7 +8455,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
if (!dev_priv->wm_disp->optimize_watermarks)
if (!dev_priv->display.funcs.wm->optimize_watermarks)
return;
state = drm_atomic_state_alloc(&dev_priv->drm);

21
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@ -8,6 +8,7 @@
#include <linux/types.h>
struct drm_i915_private;
struct intel_atomic_state;
struct intel_cdclk_funcs;
struct intel_crtc;
@ -32,6 +33,23 @@ struct intel_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
};
/* functions used for watermark calcs for display. */
struct intel_wm_funcs {
/* update_wm is for legacy wm management */
void (*update_wm)(struct drm_i915_private *dev_priv);
int (*compute_pipe_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*initial_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
};
struct intel_display {
/* Display functions */
struct {
@ -46,6 +64,9 @@ struct intel_display {
/* irq display functions */
const struct intel_hotplug_funcs *hotplug;
/* pm display functions */
const struct intel_wm_funcs *wm;
} funcs;
};

22
drivers/gpu/drm/i915/i915_drv.h
View File

@ -81,14 +81,12 @@ struct dpll;
struct drm_i915_clock_gating_funcs;
struct drm_i915_gem_object;
struct drm_i915_private;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_config;
struct intel_cdclk_state;
struct intel_cdclk_vals;
struct intel_color_funcs;
struct intel_connector;
struct intel_crtc;
struct intel_dp;
struct intel_encoder;
struct intel_fbdev;
@ -157,23 +155,6 @@ struct sdvo_device_mapping {
u8 ddc_pin;
};
/* functions used for watermark calcs for display. */
struct drm_i915_wm_disp_funcs {
/* update_wm is for legacy wm management */
void (*update_wm)(struct drm_i915_private *dev_priv);
int (*compute_pipe_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*initial_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
};
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@ -505,9 +486,6 @@ struct drm_i915_private {
/* pm private clock gating functions */
const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
/* pm display functions */
const struct drm_i915_wm_disp_funcs *wm_disp;
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;

42
drivers/gpu/drm/i915/intel_pm.c
View File

@ -8197,18 +8197,18 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
}
}
static const struct drm_i915_wm_disp_funcs skl_wm_funcs = {
static const struct intel_wm_funcs skl_wm_funcs = {
.compute_global_watermarks = skl_compute_wm,
};
static const struct drm_i915_wm_disp_funcs ilk_wm_funcs = {
static const struct intel_wm_funcs ilk_wm_funcs = {
.compute_pipe_wm = ilk_compute_pipe_wm,
.compute_intermediate_wm = ilk_compute_intermediate_wm,
.initial_watermarks = ilk_initial_watermarks,
.optimize_watermarks = ilk_optimize_watermarks,
};
static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
static const struct intel_wm_funcs vlv_wm_funcs = {
.compute_pipe_wm = vlv_compute_pipe_wm,
.compute_intermediate_wm = vlv_compute_intermediate_wm,
.initial_watermarks = vlv_initial_watermarks,
@ -8216,30 +8216,30 @@ static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
.atomic_update_watermarks = vlv_atomic_update_fifo,
};
static const struct drm_i915_wm_disp_funcs g4x_wm_funcs = {
static const struct intel_wm_funcs g4x_wm_funcs = {
.compute_pipe_wm = g4x_compute_pipe_wm,
.compute_intermediate_wm = g4x_compute_intermediate_wm,
.initial_watermarks = g4x_initial_watermarks,
.optimize_watermarks = g4x_optimize_watermarks,
};
static const struct drm_i915_wm_disp_funcs pnv_wm_funcs = {
static const struct intel_wm_funcs pnv_wm_funcs = {
.update_wm = pnv_update_wm,
};
static const struct drm_i915_wm_disp_funcs i965_wm_funcs = {
static const struct intel_wm_funcs i965_wm_funcs = {
.update_wm = i965_update_wm,
};
static const struct drm_i915_wm_disp_funcs i9xx_wm_funcs = {
static const struct intel_wm_funcs i9xx_wm_funcs = {
.update_wm = i9xx_update_wm,
};
static const struct drm_i915_wm_disp_funcs i845_wm_funcs = {
static const struct intel_wm_funcs i845_wm_funcs = {
.update_wm = i845_update_wm,
};
static const struct drm_i915_wm_disp_funcs nop_funcs = {
static const struct intel_wm_funcs nop_funcs = {
};
/* Set up chip specific power management-related functions */
@ -8256,7 +8256,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (DISPLAY_VER(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
dev_priv->wm_disp = &skl_wm_funcs;
dev_priv->display.funcs.wm = &skl_wm_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
@ -8264,19 +8264,19 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->wm_disp = &ilk_wm_funcs;
dev_priv->display.funcs.wm = &ilk_wm_funcs;
} else {
drm_dbg_kms(&dev_priv->drm,
"Failed to read display plane latency. "
"Disable CxSR\n");
dev_priv->wm_disp = &nop_funcs;
dev_priv->display.funcs.wm = &nop_funcs;
}
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv);
dev_priv->wm_disp = &vlv_wm_funcs;
dev_priv->display.funcs.wm = &vlv_wm_funcs;
} else if (IS_G4X(dev_priv)) {
g4x_setup_wm_latency(dev_priv);
dev_priv->wm_disp = &g4x_wm_funcs;
dev_priv->display.funcs.wm = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
dev_priv->is_ddr3,
@ -8290,22 +8290,22 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq, dev_priv->mem_freq);
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
dev_priv->wm_disp = &nop_funcs;
dev_priv->display.funcs.wm = &nop_funcs;
} else
dev_priv->wm_disp = &pnv_wm_funcs;
dev_priv->display.funcs.wm = &pnv_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 4) {
dev_priv->wm_disp = &i965_wm_funcs;
dev_priv->display.funcs.wm = &i965_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 3) {
dev_priv->wm_disp = &i9xx_wm_funcs;
dev_priv->display.funcs.wm = &i9xx_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1)
dev_priv->wm_disp = &i845_wm_funcs;
dev_priv->display.funcs.wm = &i845_wm_funcs;
else
dev_priv->wm_disp = &i9xx_wm_funcs;
dev_priv->display.funcs.wm = &i9xx_wm_funcs;
} else {
drm_err(&dev_priv->drm,
"unexpected fall-through in %s\n", __func__);
dev_priv->wm_disp = &nop_funcs;
dev_priv->display.funcs.wm = &nop_funcs;
}
}