arm64: dts: renesas: r8a77965: Add FCPF and FCPV instances
The FCPs handle the interface between various IP cores and memory. Add the instances related to the FDPs and VSP2s. Based on a similar patch of the R8A7796 device tree by Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Kieran: Rebase to top of tree] Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -10,6 +10,7 @@
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a77965-sysc.h>
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#define CPG_AUDIO_CLK_I 10
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@ -1000,6 +1001,46 @@
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/* placeholder */
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};
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fcpf0: fcp@fe950000 {
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compatible = "renesas,fcpf";
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reg = <0 0xfe950000 0 0x200>;
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clocks = <&cpg CPG_MOD 615>;
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power-domains = <&sysc R8A77965_PD_A3VP>;
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resets = <&cpg 615>;
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};
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fcpvb0: fcp@fe96f000 {
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compatible = "renesas,fcpv";
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reg = <0 0xfe96f000 0 0x200>;
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clocks = <&cpg CPG_MOD 607>;
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power-domains = <&sysc R8A77965_PD_A3VP>;
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resets = <&cpg 607>;
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};
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fcpvi0: fcp@fe9af000 {
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compatible = "renesas,fcpv";
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reg = <0 0xfe9af000 0 0x200>;
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clocks = <&cpg CPG_MOD 611>;
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power-domains = <&sysc R8A77965_PD_A3VP>;
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resets = <&cpg 611>;
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};
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fcpvd0: fcp@fea27000 {
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compatible = "renesas,fcpv";
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reg = <0 0xfea27000 0 0x200>;
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clocks = <&cpg CPG_MOD 603>;
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power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
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resets = <&cpg 603>;
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};
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fcpvd1: fcp@fea2f000 {
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compatible = "renesas,fcpv";
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reg = <0 0xfea2f000 0 0x200>;
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clocks = <&cpg CPG_MOD 602>;
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power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
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resets = <&cpg 602>;
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};
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csi20: csi2@fea80000 {
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reg = <0 0xfea80000 0 0x10000>;
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/* placeholder */
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