EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC
This driver supports Intel client SoC with integrated memory controller using In-Band ECC(IBECC). The memory correctable and uncorrectable errors are reported via NMIs. The driver handles the NMIs and decodes the memory error address to platform specific address. The first IBECC-supported SoC is Elkhart Lake. [Tony: s/#include <linux/nmi.h>/#include <asm/nmi.h>/ to fix randconfig build] Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Qiuxu Zhuo
Tony Luck
parent
3b20369313
commit
10590a9d4f
@ -269,6 +269,15 @@ config EDAC_PND2
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first used on the Apollo Lake platform and Denverton
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micro-server but may appear on others in the future.
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config EDAC_IGEN6
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tristate "Intel client SoC Integrated MC"
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depends on PCI && X86_64 && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
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help
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Support for error detection and correction on the Intel
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client SoC Integrated Memory Controller using In-Band ECC IP.
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This In-Band ECC is first used on the Elkhart Lake SoC but
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may appear on others in the future.
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config EDAC_MPC85XX
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bool "Freescale MPC83xx / MPC85xx"
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depends on FSL_SOC && EDAC=y
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@ -32,6 +32,7 @@ obj-$(CONFIG_EDAC_I7300) += i7300_edac.o
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obj-$(CONFIG_EDAC_I7CORE) += i7core_edac.o
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obj-$(CONFIG_EDAC_SBRIDGE) += sb_edac.o
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obj-$(CONFIG_EDAC_PND2) += pnd2_edac.o
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obj-$(CONFIG_EDAC_IGEN6) += igen6_edac.o
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obj-$(CONFIG_EDAC_E7XXX) += e7xxx_edac.o
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obj-$(CONFIG_EDAC_E752X) += e752x_edac.o
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obj-$(CONFIG_EDAC_I82443BXGX) += i82443bxgx_edac.o
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918
drivers/edac/igen6_edac.c
Normal file
918
drivers/edac/igen6_edac.c
Normal file
@ -0,0 +1,918 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Intel client SoC with integrated memory controller using IBECC
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*
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* Copyright (C) 2020 Intel Corporation
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*
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* The In-Band ECC (IBECC) IP provides ECC protection to all or specific
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* regions of the physical memory space. It's used for memory controllers
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* that don't support the out-of-band ECC which often needs an additional
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* storage device to each channel for storing ECC data.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/irq_work.h>
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#include <linux/llist.h>
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#include <linux/genalloc.h>
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#include <linux/edac.h>
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#include <linux/bits.h>
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#include <linux/io.h>
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#include <asm/mach_traps.h>
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#include <asm/nmi.h>
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#include "edac_mc.h"
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#include "edac_module.h"
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#define IGEN6_REVISION "v2.4"
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#define EDAC_MOD_STR "igen6_edac"
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#define IGEN6_NMI_NAME "igen6_ibecc"
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/* Debug macros */
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#define igen6_printk(level, fmt, arg...) \
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edac_printk(level, "igen6", fmt, ##arg)
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#define igen6_mc_printk(mci, level, fmt, arg...) \
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edac_mc_chipset_printk(mci, level, "igen6", fmt, ##arg)
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#define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))
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#define NUM_IMC 1 /* Max memory controllers */
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#define NUM_CHANNELS 2 /* Max channels */
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#define NUM_DIMMS 2 /* Max DIMMs per channel */
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#define _4GB BIT_ULL(32)
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/* Size of physical memory */
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#define TOM_OFFSET 0xa0
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/* Top of low usable DRAM */
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#define TOLUD_OFFSET 0xbc
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/* Capability register C */
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#define CAPID_C_OFFSET 0xec
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#define CAPID_C_IBECC BIT(15)
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/* Error Status */
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#define ERRSTS_OFFSET 0xc8
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#define ERRSTS_CE BIT_ULL(6)
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#define ERRSTS_UE BIT_ULL(7)
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/* Error Command */
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#define ERRCMD_OFFSET 0xca
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#define ERRCMD_CE BIT_ULL(6)
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#define ERRCMD_UE BIT_ULL(7)
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/* IBECC MMIO base address */
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#define IBECC_BASE (res_cfg->ibecc_base)
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#define IBECC_ACTIVATE_OFFSET IBECC_BASE
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#define IBECC_ACTIVATE_EN BIT(0)
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/* IBECC error log */
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#define ECC_ERROR_LOG_OFFSET (IBECC_BASE + 0x170)
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#define ECC_ERROR_LOG_CE BIT_ULL(62)
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#define ECC_ERROR_LOG_UE BIT_ULL(63)
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#define ECC_ERROR_LOG_ADDR_SHIFT 5
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#define ECC_ERROR_LOG_ADDR(v) GET_BITFIELD(v, 5, 38)
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#define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61)
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/* Host MMIO base address */
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#define MCHBAR_OFFSET 0x48
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#define MCHBAR_EN BIT_ULL(0)
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#define MCHBAR_BASE(v) (GET_BITFIELD(v, 16, 38) << 16)
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#define MCHBAR_SIZE 0x10000
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/* Parameters for the channel decode stage */
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#define MAD_INTER_CHANNEL_OFFSET 0x5000
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#define MAD_INTER_CHANNEL_DDR_TYPE(v) GET_BITFIELD(v, 0, 2)
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#define MAD_INTER_CHANNEL_ECHM(v) GET_BITFIELD(v, 3, 3)
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#define MAD_INTER_CHANNEL_CH_L_MAP(v) GET_BITFIELD(v, 4, 4)
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#define MAD_INTER_CHANNEL_CH_S_SIZE(v) ((u64)GET_BITFIELD(v, 12, 19) << 29)
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/* Parameters for DRAM decode stage */
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#define MAD_INTRA_CH0_OFFSET 0x5004
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#define MAD_INTRA_CH_DIMM_L_MAP(v) GET_BITFIELD(v, 0, 0)
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/* DIMM characteristics */
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#define MAD_DIMM_CH0_OFFSET 0x500c
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#define MAD_DIMM_CH_DIMM_L_SIZE(v) ((u64)GET_BITFIELD(v, 0, 6) << 29)
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#define MAD_DIMM_CH_DLW(v) GET_BITFIELD(v, 7, 8)
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#define MAD_DIMM_CH_DIMM_S_SIZE(v) ((u64)GET_BITFIELD(v, 16, 22) << 29)
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#define MAD_DIMM_CH_DSW(v) GET_BITFIELD(v, 24, 25)
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/* Hash for channel selection */
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#define CHANNEL_HASH_OFFSET 0X5024
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/* Hash for enhanced channel selection */
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#define CHANNEL_EHASH_OFFSET 0X5028
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#define CHANNEL_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)
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#define CHANNEL_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)
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#define CHANNEL_HASH_MODE(v) GET_BITFIELD(v, 28, 28)
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static struct res_config {
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int num_imc;
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u32 ibecc_base;
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bool (*ibecc_available)(struct pci_dev *pdev);
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/* Convert error address logged in IBECC to system physical address */
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u64 (*err_addr_to_sys_addr)(u64 eaddr);
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/* Convert error address logged in IBECC to integrated memory controller address */
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u64 (*err_addr_to_imc_addr)(u64 eaddr);
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} *res_cfg;
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struct igen6_imc {
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int mc;
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struct mem_ctl_info *mci;
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struct pci_dev *pdev;
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struct device dev;
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void __iomem *window;
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u64 ch_s_size;
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int ch_l_map;
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u64 dimm_s_size[NUM_CHANNELS];
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u64 dimm_l_size[NUM_CHANNELS];
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int dimm_l_map[NUM_CHANNELS];
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};
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static struct igen6_pvt {
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struct igen6_imc imc[NUM_IMC];
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} *igen6_pvt;
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/* The top of low usable DRAM */
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static u32 igen6_tolud;
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/* The size of physical memory */
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static u64 igen6_tom;
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struct decoded_addr {
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int mc;
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u64 imc_addr;
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u64 sys_addr;
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int channel_idx;
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u64 channel_addr;
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int sub_channel_idx;
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u64 sub_channel_addr;
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};
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struct ecclog_node {
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struct llist_node llnode;
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int mc;
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u64 ecclog;
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};
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/*
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* In the NMI handler, the driver uses the lock-less memory allocator
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* to allocate memory to store the IBECC error logs and links the logs
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* to the lock-less list. Delay printk() and the work of error reporting
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* to EDAC core in a worker.
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*/
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#define ECCLOG_POOL_SIZE PAGE_SIZE
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LLIST_HEAD(ecclog_llist);
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static struct gen_pool *ecclog_pool;
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static char ecclog_buf[ECCLOG_POOL_SIZE];
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static struct irq_work ecclog_irq_work;
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static struct work_struct ecclog_work;
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/* Compute die IDs for Elkhart Lake with IBECC */
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#define DID_EHL_SKU5 0x4514
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#define DID_EHL_SKU6 0x4528
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#define DID_EHL_SKU7 0x452a
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#define DID_EHL_SKU8 0x4516
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#define DID_EHL_SKU9 0x452c
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#define DID_EHL_SKU10 0x452e
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#define DID_EHL_SKU11 0x4532
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#define DID_EHL_SKU12 0x4518
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#define DID_EHL_SKU13 0x451a
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#define DID_EHL_SKU14 0x4534
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#define DID_EHL_SKU15 0x4536
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static bool ehl_ibecc_available(struct pci_dev *pdev)
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{
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u32 v;
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if (pci_read_config_dword(pdev, CAPID_C_OFFSET, &v))
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return false;
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return !!(CAPID_C_IBECC & v);
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}
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static u64 ehl_err_addr_to_sys_addr(u64 eaddr)
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{
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return eaddr;
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}
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static u64 ehl_err_addr_to_imc_addr(u64 eaddr)
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{
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if (eaddr < igen6_tolud)
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return eaddr;
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if (igen6_tom <= _4GB)
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return eaddr + igen6_tolud - _4GB;
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if (eaddr < _4GB)
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return eaddr + igen6_tolud - igen6_tom;
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return eaddr;
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}
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static struct res_config ehl_cfg = {
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.num_imc = 1,
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.ibecc_base = 0xdc00,
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.ibecc_available = ehl_ibecc_available,
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.err_addr_to_sys_addr = ehl_err_addr_to_sys_addr,
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.err_addr_to_imc_addr = ehl_err_addr_to_imc_addr,
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};
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static const struct pci_device_id igen6_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU5), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU6), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU7), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU8), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU9), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU10), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU11), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU12), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU13), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU14), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU15), (kernel_ulong_t)&ehl_cfg },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, igen6_pci_tbl);
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static enum dev_type get_width(int dimm_l, u32 mad_dimm)
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{
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u32 w = dimm_l ? MAD_DIMM_CH_DLW(mad_dimm) :
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MAD_DIMM_CH_DSW(mad_dimm);
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switch (w) {
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case 0:
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return DEV_X8;
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case 1:
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return DEV_X16;
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case 2:
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return DEV_X32;
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default:
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return DEV_UNKNOWN;
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}
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}
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static enum mem_type get_memory_type(u32 mad_inter)
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{
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u32 t = MAD_INTER_CHANNEL_DDR_TYPE(mad_inter);
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switch (t) {
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case 0:
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return MEM_DDR4;
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case 1:
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return MEM_DDR3;
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case 2:
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return MEM_LPDDR3;
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case 3:
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return MEM_LPDDR4;
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case 4:
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return MEM_WIO2;
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default:
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return MEM_UNKNOWN;
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}
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}
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static int decode_chan_idx(u64 addr, u64 mask, int intlv_bit)
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{
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u64 hash_addr = addr & mask, hash = 0;
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u64 intlv = (addr >> intlv_bit) & 1;
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int i;
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for (i = 6; i < 20; i++)
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hash ^= (hash_addr >> i) & 1;
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return (int)hash ^ intlv;
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}
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static u64 decode_channel_addr(u64 addr, int intlv_bit)
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{
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u64 channel_addr;
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/* Remove the interleave bit and shift upper part down to fill gap */
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channel_addr = GET_BITFIELD(addr, intlv_bit + 1, 63) << intlv_bit;
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channel_addr |= GET_BITFIELD(addr, 0, intlv_bit - 1);
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return channel_addr;
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}
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static void decode_addr(u64 addr, u32 hash, u64 s_size, int l_map,
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int *idx, u64 *sub_addr)
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{
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int intlv_bit = CHANNEL_HASH_LSB_MASK_BIT(hash) + 6;
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if (addr > 2 * s_size) {
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*sub_addr = addr - s_size;
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*idx = l_map;
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return;
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}
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if (CHANNEL_HASH_MODE(hash)) {
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*sub_addr = decode_channel_addr(addr, intlv_bit);
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*idx = decode_chan_idx(addr, CHANNEL_HASH_MASK(hash), intlv_bit);
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} else {
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*sub_addr = decode_channel_addr(addr, 6);
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*idx = GET_BITFIELD(addr, 6, 6);
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}
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}
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static int igen6_decode(struct decoded_addr *res)
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{
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struct igen6_imc *imc = &igen6_pvt->imc[res->mc];
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u64 addr = res->imc_addr, sub_addr, s_size;
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int idx, l_map;
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u32 hash;
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if (addr >= igen6_tom) {
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edac_dbg(0, "Address 0x%llx out of range\n", addr);
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return -EINVAL;
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}
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/* Decode channel */
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hash = readl(imc->window + CHANNEL_HASH_OFFSET);
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s_size = imc->ch_s_size;
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l_map = imc->ch_l_map;
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decode_addr(addr, hash, s_size, l_map, &idx, &sub_addr);
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res->channel_idx = idx;
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res->channel_addr = sub_addr;
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/* Decode sub-channel/DIMM */
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hash = readl(imc->window + CHANNEL_EHASH_OFFSET);
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s_size = imc->dimm_s_size[idx];
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l_map = imc->dimm_l_map[idx];
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decode_addr(res->channel_addr, hash, s_size, l_map, &idx, &sub_addr);
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res->sub_channel_idx = idx;
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res->sub_channel_addr = sub_addr;
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return 0;
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}
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static void igen6_output_error(struct decoded_addr *res,
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struct mem_ctl_info *mci, u64 ecclog)
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{
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enum hw_event_mc_err_type type = ecclog & ECC_ERROR_LOG_UE ?
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HW_EVENT_ERR_UNCORRECTED :
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HW_EVENT_ERR_CORRECTED;
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edac_mc_handle_error(type, mci, 1,
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res->sys_addr >> PAGE_SHIFT,
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res->sys_addr & ~PAGE_MASK,
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ECC_ERROR_LOG_SYND(ecclog),
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res->channel_idx, res->sub_channel_idx,
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-1, "", "");
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}
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static struct gen_pool *ecclog_gen_pool_create(void)
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{
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struct gen_pool *pool;
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pool = gen_pool_create(ilog2(sizeof(struct ecclog_node)), -1);
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if (!pool)
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return NULL;
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if (gen_pool_add(pool, (unsigned long)ecclog_buf, ECCLOG_POOL_SIZE, -1)) {
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gen_pool_destroy(pool);
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return NULL;
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}
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return pool;
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}
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static int ecclog_gen_pool_add(int mc, u64 ecclog)
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{
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struct ecclog_node *node;
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node = (void *)gen_pool_alloc(ecclog_pool, sizeof(*node));
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if (!node)
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return -ENOMEM;
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node->mc = mc;
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node->ecclog = ecclog;
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llist_add(&node->llnode, &ecclog_llist);
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return 0;
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}
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/*
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* Either the memory-mapped I/O status register ECC_ERROR_LOG or the PCI
|
||||
* configuration space status register ERRSTS can indicate whether a
|
||||
* correctable error or an uncorrectable error occurred. We only use the
|
||||
* ECC_ERROR_LOG register to check error type, but need to clear both
|
||||
* registers to enable future error events.
|
||||
*/
|
||||
static u64 ecclog_read_and_clear(struct igen6_imc *imc)
|
||||
{
|
||||
u64 ecclog = readq(imc->window + ECC_ERROR_LOG_OFFSET);
|
||||
|
||||
if (ecclog & (ECC_ERROR_LOG_CE | ECC_ERROR_LOG_UE)) {
|
||||
/* Clear CE/UE bits by writing 1s */
|
||||
writeq(ecclog, imc->window + ECC_ERROR_LOG_OFFSET);
|
||||
return ecclog;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void errsts_clear(struct igen6_imc *imc)
|
||||
{
|
||||
u16 errsts;
|
||||
|
||||
if (pci_read_config_word(imc->pdev, ERRSTS_OFFSET, &errsts)) {
|
||||
igen6_printk(KERN_ERR, "Failed to read ERRSTS\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clear CE/UE bits by writing 1s */
|
||||
if (errsts & (ERRSTS_CE | ERRSTS_UE))
|
||||
pci_write_config_word(imc->pdev, ERRSTS_OFFSET, errsts);
|
||||
}
|
||||
|
||||
static int errcmd_enable_error_reporting(bool enable)
|
||||
{
|
||||
struct igen6_imc *imc = &igen6_pvt->imc[0];
|
||||
u16 errcmd;
|
||||
int rc;
|
||||
|
||||
rc = pci_read_config_word(imc->pdev, ERRCMD_OFFSET, &errcmd);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (enable)
|
||||
errcmd |= ERRCMD_CE | ERRSTS_UE;
|
||||
else
|
||||
errcmd &= ~(ERRCMD_CE | ERRSTS_UE);
|
||||
|
||||
rc = pci_write_config_word(imc->pdev, ERRCMD_OFFSET, errcmd);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ecclog_handler(void)
|
||||
{
|
||||
struct igen6_imc *imc;
|
||||
int i, n = 0;
|
||||
u64 ecclog;
|
||||
|
||||
for (i = 0; i < res_cfg->num_imc; i++) {
|
||||
imc = &igen6_pvt->imc[i];
|
||||
|
||||
/* errsts_clear() isn't NMI-safe. Delay it in the IRQ context */
|
||||
|
||||
ecclog = ecclog_read_and_clear(imc);
|
||||
if (!ecclog)
|
||||
continue;
|
||||
|
||||
if (!ecclog_gen_pool_add(i, ecclog))
|
||||
irq_work_queue(&ecclog_irq_work);
|
||||
|
||||
n++;
|
||||
}
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
static void ecclog_work_cb(struct work_struct *work)
|
||||
{
|
||||
struct ecclog_node *node, *tmp;
|
||||
struct mem_ctl_info *mci;
|
||||
struct llist_node *head;
|
||||
struct decoded_addr res;
|
||||
u64 eaddr;
|
||||
|
||||
head = llist_del_all(&ecclog_llist);
|
||||
if (!head)
|
||||
return;
|
||||
|
||||
llist_for_each_entry_safe(node, tmp, head, llnode) {
|
||||
memset(&res, 0, sizeof(res));
|
||||
eaddr = ECC_ERROR_LOG_ADDR(node->ecclog) <<
|
||||
ECC_ERROR_LOG_ADDR_SHIFT;
|
||||
res.mc = node->mc;
|
||||
res.sys_addr = res_cfg->err_addr_to_sys_addr(eaddr);
|
||||
res.imc_addr = res_cfg->err_addr_to_imc_addr(eaddr);
|
||||
|
||||
mci = igen6_pvt->imc[res.mc].mci;
|
||||
|
||||
edac_dbg(2, "MC %d, ecclog = 0x%llx\n", node->mc, node->ecclog);
|
||||
igen6_mc_printk(mci, KERN_DEBUG, "HANDLING IBECC MEMORY ERROR\n");
|
||||
igen6_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", res.sys_addr);
|
||||
|
||||
if (!igen6_decode(&res))
|
||||
igen6_output_error(&res, mci, node->ecclog);
|
||||
|
||||
gen_pool_free(ecclog_pool, (unsigned long)node, sizeof(*node));
|
||||
}
|
||||
}
|
||||
|
||||
static void ecclog_irq_work_cb(struct irq_work *irq_work)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < res_cfg->num_imc; i++)
|
||||
errsts_clear(&igen6_pvt->imc[i]);
|
||||
|
||||
if (!llist_empty(&ecclog_llist))
|
||||
schedule_work(&ecclog_work);
|
||||
}
|
||||
|
||||
static int ecclog_nmi_handler(unsigned int cmd, struct pt_regs *regs)
|
||||
{
|
||||
unsigned char reason;
|
||||
|
||||
if (!ecclog_handler())
|
||||
return NMI_DONE;
|
||||
|
||||
/*
|
||||
* Both In-Band ECC correctable error and uncorrectable error are
|
||||
* reported by SERR# NMI. The NMI generic code (see pci_serr_error())
|
||||
* doesn't clear the bit NMI_REASON_CLEAR_SERR (in port 0x61) to
|
||||
* re-enable the SERR# NMI after NMI handling. So clear this bit here
|
||||
* to re-enable SERR# NMI for receiving future In-Band ECC errors.
|
||||
*/
|
||||
reason = x86_platform.get_nmi_reason() & NMI_REASON_CLEAR_MASK;
|
||||
reason |= NMI_REASON_CLEAR_SERR;
|
||||
outb(reason, NMI_REASON_PORT);
|
||||
reason &= ~NMI_REASON_CLEAR_SERR;
|
||||
outb(reason, NMI_REASON_PORT);
|
||||
|
||||
return NMI_HANDLED;
|
||||
}
|
||||
|
||||
static bool igen6_check_ecc(struct igen6_imc *imc)
|
||||
{
|
||||
u32 activate = readl(imc->window + IBECC_ACTIVATE_OFFSET);
|
||||
|
||||
return !!(activate & IBECC_ACTIVATE_EN);
|
||||
}
|
||||
|
||||
static int igen6_get_dimm_config(struct mem_ctl_info *mci)
|
||||
{
|
||||
struct igen6_imc *imc = mci->pvt_info;
|
||||
u32 mad_inter, mad_intra, mad_dimm;
|
||||
int i, j, ndimms, mc = imc->mc;
|
||||
struct dimm_info *dimm;
|
||||
enum mem_type mtype;
|
||||
enum dev_type dtype;
|
||||
u64 dsize;
|
||||
bool ecc;
|
||||
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
mad_inter = readl(imc->window + MAD_INTER_CHANNEL_OFFSET);
|
||||
mtype = get_memory_type(mad_inter);
|
||||
ecc = igen6_check_ecc(imc);
|
||||
imc->ch_s_size = MAD_INTER_CHANNEL_CH_S_SIZE(mad_inter);
|
||||
imc->ch_l_map = MAD_INTER_CHANNEL_CH_L_MAP(mad_inter);
|
||||
|
||||
for (i = 0; i < NUM_CHANNELS; i++) {
|
||||
mad_intra = readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4);
|
||||
mad_dimm = readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4);
|
||||
|
||||
imc->dimm_l_size[i] = MAD_DIMM_CH_DIMM_L_SIZE(mad_dimm);
|
||||
imc->dimm_s_size[i] = MAD_DIMM_CH_DIMM_S_SIZE(mad_dimm);
|
||||
imc->dimm_l_map[i] = MAD_INTRA_CH_DIMM_L_MAP(mad_intra);
|
||||
ndimms = 0;
|
||||
|
||||
for (j = 0; j < NUM_DIMMS; j++) {
|
||||
dimm = edac_get_dimm(mci, i, j, 0);
|
||||
|
||||
if (j ^ imc->dimm_l_map[i]) {
|
||||
dtype = get_width(0, mad_dimm);
|
||||
dsize = imc->dimm_s_size[i];
|
||||
} else {
|
||||
dtype = get_width(1, mad_dimm);
|
||||
dsize = imc->dimm_l_size[i];
|
||||
}
|
||||
|
||||
if (!dsize)
|
||||
continue;
|
||||
|
||||
dimm->grain = 64;
|
||||
dimm->mtype = mtype;
|
||||
dimm->dtype = dtype;
|
||||
dimm->nr_pages = MiB_TO_PAGES(dsize >> 20);
|
||||
dimm->edac_mode = EDAC_SECDED;
|
||||
snprintf(dimm->label, sizeof(dimm->label),
|
||||
"MC#%d_Chan#%d_DIMM#%d", mc, i, j);
|
||||
edac_dbg(0, "MC %d, Channel %d, DIMM %d, Size %llu MiB (%u pages)\n",
|
||||
mc, i, j, dsize >> 20, dimm->nr_pages);
|
||||
|
||||
ndimms++;
|
||||
}
|
||||
|
||||
if (ndimms && !ecc) {
|
||||
igen6_printk(KERN_ERR, "MC%d In-Band ECC is disabled\n", mc);
|
||||
return -ENODEV;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
static void igen6_reg_dump(struct igen6_imc *imc)
|
||||
{
|
||||
int i;
|
||||
|
||||
edac_dbg(2, "CHANNEL_HASH : 0x%x\n",
|
||||
readl(imc->window + CHANNEL_HASH_OFFSET));
|
||||
edac_dbg(2, "CHANNEL_EHASH : 0x%x\n",
|
||||
readl(imc->window + CHANNEL_EHASH_OFFSET));
|
||||
edac_dbg(2, "MAD_INTER_CHANNEL: 0x%x\n",
|
||||
readl(imc->window + MAD_INTER_CHANNEL_OFFSET));
|
||||
edac_dbg(2, "ECC_ERROR_LOG : 0x%llx\n",
|
||||
readq(imc->window + ECC_ERROR_LOG_OFFSET));
|
||||
|
||||
for (i = 0; i < NUM_CHANNELS; i++) {
|
||||
edac_dbg(2, "MAD_INTRA_CH%d : 0x%x\n", i,
|
||||
readl(imc->window + MAD_INTRA_CH0_OFFSET + i * 4));
|
||||
edac_dbg(2, "MAD_DIMM_CH%d : 0x%x\n", i,
|
||||
readl(imc->window + MAD_DIMM_CH0_OFFSET + i * 4));
|
||||
}
|
||||
edac_dbg(2, "TOLUD : 0x%x", igen6_tolud);
|
||||
edac_dbg(2, "TOM : 0x%llx", igen6_tom);
|
||||
}
|
||||
#else
|
||||
static void igen6_reg_dump(struct igen6_imc *imc) {}
|
||||
#endif
|
||||
|
||||
static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar)
|
||||
{
|
||||
union {
|
||||
u64 v;
|
||||
struct {
|
||||
u32 v_lo;
|
||||
u32 v_hi;
|
||||
};
|
||||
} u;
|
||||
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
if (!res_cfg->ibecc_available(pdev)) {
|
||||
edac_dbg(2, "No In-Band ECC IP\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (pci_read_config_dword(pdev, TOLUD_OFFSET, &igen6_tolud)) {
|
||||
igen6_printk(KERN_ERR, "Failed to read TOLUD\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
igen6_tolud &= GENMASK(31, 20);
|
||||
|
||||
if (pci_read_config_dword(pdev, TOM_OFFSET, &u.v_lo)) {
|
||||
igen6_printk(KERN_ERR, "Failed to read lower TOM\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (pci_read_config_dword(pdev, TOM_OFFSET + 4, &u.v_hi)) {
|
||||
igen6_printk(KERN_ERR, "Failed to read upper TOM\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
igen6_tom = u.v & GENMASK_ULL(38, 20);
|
||||
|
||||
if (pci_read_config_dword(pdev, MCHBAR_OFFSET, &u.v_lo)) {
|
||||
igen6_printk(KERN_ERR, "Failed to read lower MCHBAR\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (pci_read_config_dword(pdev, MCHBAR_OFFSET + 4, &u.v_hi)) {
|
||||
igen6_printk(KERN_ERR, "Failed to read upper MCHBAR\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (!(u.v & MCHBAR_EN)) {
|
||||
igen6_printk(KERN_ERR, "MCHBAR is disabled\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
*mchbar = MCHBAR_BASE(u.v);
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev)
|
||||
{
|
||||
struct edac_mc_layer layers[2];
|
||||
struct mem_ctl_info *mci;
|
||||
struct igen6_imc *imc;
|
||||
void __iomem *window;
|
||||
int rc;
|
||||
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
mchbar += mc * MCHBAR_SIZE;
|
||||
window = ioremap(mchbar, MCHBAR_SIZE);
|
||||
if (!window) {
|
||||
igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
layers[0].type = EDAC_MC_LAYER_CHANNEL;
|
||||
layers[0].size = NUM_CHANNELS;
|
||||
layers[0].is_virt_csrow = false;
|
||||
layers[1].type = EDAC_MC_LAYER_SLOT;
|
||||
layers[1].size = NUM_DIMMS;
|
||||
layers[1].is_virt_csrow = true;
|
||||
|
||||
mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);
|
||||
if (!mci) {
|
||||
rc = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
mci->ctl_name = kasprintf(GFP_KERNEL, "Intel_client_SoC MC#%d", mc);
|
||||
if (!mci->ctl_name) {
|
||||
rc = -ENOMEM;
|
||||
goto fail2;
|
||||
}
|
||||
|
||||
mci->mtype_cap = MEM_FLAG_LPDDR4 | MEM_FLAG_DDR4;
|
||||
mci->edac_ctl_cap = EDAC_FLAG_SECDED;
|
||||
mci->edac_cap = EDAC_FLAG_SECDED;
|
||||
mci->mod_name = EDAC_MOD_STR;
|
||||
mci->dev_name = pci_name(pdev);
|
||||
mci->pvt_info = &igen6_pvt->imc[mc];
|
||||
|
||||
imc = mci->pvt_info;
|
||||
device_initialize(&imc->dev);
|
||||
/*
|
||||
* EDAC core uses mci->pdev(pointer of structure device) as
|
||||
* memory controller ID. The client SoCs attach one or more
|
||||
* memory controllers to single pci_dev (single pci_dev->dev
|
||||
* can be for multiple memory controllers).
|
||||
*
|
||||
* To make mci->pdev unique, assign pci_dev->dev to mci->pdev
|
||||
* for the first memory controller and assign a unique imc->dev
|
||||
* to mci->pdev for each non-first memory controller.
|
||||
*/
|
||||
mci->pdev = mc ? &imc->dev : &pdev->dev;
|
||||
imc->mc = mc;
|
||||
imc->pdev = pdev;
|
||||
imc->window = window;
|
||||
|
||||
igen6_reg_dump(imc);
|
||||
|
||||
rc = igen6_get_dimm_config(mci);
|
||||
if (rc)
|
||||
goto fail3;
|
||||
|
||||
rc = edac_mc_add_mc(mci);
|
||||
if (rc) {
|
||||
igen6_printk(KERN_ERR, "Failed to register mci#%d\n", mc);
|
||||
goto fail3;
|
||||
}
|
||||
|
||||
imc->mci = mci;
|
||||
return 0;
|
||||
fail3:
|
||||
kfree(mci->ctl_name);
|
||||
fail2:
|
||||
edac_mc_free(mci);
|
||||
fail:
|
||||
iounmap(window);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void igen6_unregister_mcis(void)
|
||||
{
|
||||
struct mem_ctl_info *mci;
|
||||
struct igen6_imc *imc;
|
||||
int i;
|
||||
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
for (i = 0; i < res_cfg->num_imc; i++) {
|
||||
imc = &igen6_pvt->imc[i];
|
||||
mci = imc->mci;
|
||||
if (!mci)
|
||||
continue;
|
||||
|
||||
edac_mc_del_mc(mci->pdev);
|
||||
kfree(mci->ctl_name);
|
||||
edac_mc_free(mci);
|
||||
iounmap(imc->window);
|
||||
}
|
||||
}
|
||||
|
||||
static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
u64 mchbar;
|
||||
int i, rc;
|
||||
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
igen6_pvt = kzalloc(sizeof(*igen6_pvt), GFP_KERNEL);
|
||||
if (!igen6_pvt)
|
||||
return -ENOMEM;
|
||||
|
||||
res_cfg = (struct res_config *)ent->driver_data;
|
||||
|
||||
rc = igen6_pci_setup(pdev, &mchbar);
|
||||
if (rc)
|
||||
goto fail;
|
||||
|
||||
for (i = 0; i < res_cfg->num_imc; i++) {
|
||||
rc = igen6_register_mci(i, mchbar, pdev);
|
||||
if (rc)
|
||||
goto fail2;
|
||||
}
|
||||
|
||||
ecclog_pool = ecclog_gen_pool_create();
|
||||
if (!ecclog_pool) {
|
||||
rc = -ENOMEM;
|
||||
goto fail2;
|
||||
}
|
||||
|
||||
INIT_WORK(&ecclog_work, ecclog_work_cb);
|
||||
init_irq_work(&ecclog_irq_work, ecclog_irq_work_cb);
|
||||
|
||||
/* Check if any pending errors before registering the NMI handler */
|
||||
ecclog_handler();
|
||||
|
||||
rc = register_nmi_handler(NMI_SERR, ecclog_nmi_handler,
|
||||
0, IGEN6_NMI_NAME);
|
||||
if (rc) {
|
||||
igen6_printk(KERN_ERR, "Failed to register NMI handler\n");
|
||||
goto fail3;
|
||||
}
|
||||
|
||||
/* Enable error reporting */
|
||||
rc = errcmd_enable_error_reporting(true);
|
||||
if (rc) {
|
||||
igen6_printk(KERN_ERR, "Failed to enable error reporting\n");
|
||||
goto fail4;
|
||||
}
|
||||
|
||||
return 0;
|
||||
fail4:
|
||||
unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
|
||||
fail3:
|
||||
gen_pool_destroy(ecclog_pool);
|
||||
fail2:
|
||||
igen6_unregister_mcis();
|
||||
fail:
|
||||
kfree(igen6_pvt);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void igen6_remove(struct pci_dev *pdev)
|
||||
{
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
errcmd_enable_error_reporting(false);
|
||||
unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME);
|
||||
irq_work_sync(&ecclog_irq_work);
|
||||
flush_work(&ecclog_work);
|
||||
gen_pool_destroy(ecclog_pool);
|
||||
igen6_unregister_mcis();
|
||||
kfree(igen6_pvt);
|
||||
}
|
||||
|
||||
static struct pci_driver igen6_driver = {
|
||||
.name = EDAC_MOD_STR,
|
||||
.probe = igen6_probe,
|
||||
.remove = igen6_remove,
|
||||
.id_table = igen6_pci_tbl,
|
||||
};
|
||||
|
||||
static int __init igen6_init(void)
|
||||
{
|
||||
const char *owner;
|
||||
int rc;
|
||||
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
owner = edac_get_owner();
|
||||
if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
|
||||
return -ENODEV;
|
||||
|
||||
edac_op_state = EDAC_OPSTATE_NMI;
|
||||
|
||||
rc = pci_register_driver(&igen6_driver);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
igen6_printk(KERN_INFO, "%s\n", IGEN6_REVISION);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit igen6_exit(void)
|
||||
{
|
||||
edac_dbg(2, "\n");
|
||||
|
||||
pci_unregister_driver(&igen6_driver);
|
||||
}
|
||||
|
||||
module_init(igen6_init);
|
||||
module_exit(igen6_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Qiuxu Zhuo");
|
||||
MODULE_DESCRIPTION("MC Driver for Intel client SoC using In-Band ECC");
|
||||
Loading…
Reference in New Issue
Block a user