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ASoC: fsl_xcvr: Add Counter registers

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These counter registers are part of register list,
add them to complete the register map

- DMAC counter control registers
- Data path Timestamp counter register
- Data path bit counter register
- Data path bit count timestamp register
- Data path bit read timestamp register

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1666940627-7611-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang 2022-10-28 15:03:47 +08:00 committed by Mark Brown
parent ce992ff38e
commit 107d170dc4
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
2 changed files with 61 additions and 0 deletions
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40
sound/soc/fsl/fsl_xcvr.c
View File

@ -934,6 +934,14 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = {
{ FSL_XCVR_RX_DPTH_CTRL_SET, 0x00002C89 },
{ FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00002C89 },
{ FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00002C89 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
{ FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_BCR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
{ FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CTRL, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 },
@ -944,6 +952,14 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = {
{ FSL_XCVR_TX_CS_DATA_3, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_4, 0x00000000 },
{ FSL_XCVR_TX_CS_DATA_5, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
{ FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_BCR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
{ FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
{ FSL_XCVR_DEBUG_REG_0, 0x00000000 },
{ FSL_XCVR_DEBUG_REG_1, 0x00000000 },
};
@ -975,6 +991,14 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
case FSL_XCVR_RX_DPTH_CTRL_SET:
case FSL_XCVR_RX_DPTH_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CTRL_TOG:
case FSL_XCVR_RX_DPTH_CNTR_CTRL:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
case FSL_XCVR_RX_DPTH_TSCR:
case FSL_XCVR_RX_DPTH_BCR:
case FSL_XCVR_RX_DPTH_BCTR:
case FSL_XCVR_RX_DPTH_BCRR:
case FSL_XCVR_TX_DPTH_CTRL:
case FSL_XCVR_TX_DPTH_CTRL_SET:
case FSL_XCVR_TX_DPTH_CTRL_CLR:
@ -985,6 +1009,14 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
case FSL_XCVR_TX_CS_DATA_3:
case FSL_XCVR_TX_CS_DATA_4:
case FSL_XCVR_TX_CS_DATA_5:
case FSL_XCVR_TX_DPTH_CNTR_CTRL:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
case FSL_XCVR_TX_DPTH_TSCR:
case FSL_XCVR_TX_DPTH_BCR:
case FSL_XCVR_TX_DPTH_BCTR:
case FSL_XCVR_TX_DPTH_BCRR:
case FSL_XCVR_DEBUG_REG_0:
case FSL_XCVR_DEBUG_REG_1:
return true;
@ -1017,6 +1049,10 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
case FSL_XCVR_RX_DPTH_CTRL_SET:
case FSL_XCVR_RX_DPTH_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CTRL_TOG:
case FSL_XCVR_RX_DPTH_CNTR_CTRL:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
case FSL_XCVR_TX_DPTH_CTRL_SET:
case FSL_XCVR_TX_DPTH_CTRL_CLR:
case FSL_XCVR_TX_DPTH_CTRL_TOG:
@ -1026,6 +1062,10 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
case FSL_XCVR_TX_CS_DATA_3:
case FSL_XCVR_TX_CS_DATA_4:
case FSL_XCVR_TX_CS_DATA_5:
case FSL_XCVR_TX_DPTH_CNTR_CTRL:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
return true;
default:
return false;

21
sound/soc/fsl/fsl_xcvr.h
View File

@ -49,6 +49,16 @@
#define FSL_XCVR_RX_DPTH_CTRL_CLR 0x188
#define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c
#define FSL_XCVR_RX_DPTH_CNTR_CTRL 0x1C0
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET 0x1C4
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR 0x1C8
#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG 0x1CC
#define FSL_XCVR_RX_DPTH_TSCR 0x1D0
#define FSL_XCVR_RX_DPTH_BCR 0x1D4
#define FSL_XCVR_RX_DPTH_BCTR 0x1D8
#define FSL_XCVR_RX_DPTH_BCRR 0x1DC
#define FSL_XCVR_TX_DPTH_CTRL 0x220 /* TX datapath ctrl reg */
#define FSL_XCVR_TX_DPTH_CTRL_SET 0x224
#define FSL_XCVR_TX_DPTH_CTRL_CLR 0x228
@ -59,6 +69,17 @@
#define FSL_XCVR_TX_CS_DATA_3 0x23C
#define FSL_XCVR_TX_CS_DATA_4 0x240
#define FSL_XCVR_TX_CS_DATA_5 0x244
#define FSL_XCVR_TX_DPTH_CNTR_CTRL 0x260
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_SET 0x264
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR 0x268
#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG 0x26C
#define FSL_XCVR_TX_DPTH_TSCR 0x270
#define FSL_XCVR_TX_DPTH_BCR 0x274
#define FSL_XCVR_TX_DPTH_BCTR 0x278
#define FSL_XCVR_TX_DPTH_BCRR 0x27C
#define FSL_XCVR_DEBUG_REG_0 0x2E0
#define FSL_XCVR_DEBUG_REG_1 0x2F0