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drm/nouveau/gr: switch to subdev printk macros

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:13 +10:00
parent e5c5e4f5d3
commit 109c2f2f1c
10 changed files with 339 additions and 302 deletions
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1
drivers/gpu/drm/nouveau/include/nvkm/core/enum.h
View File

@ -17,6 +17,5 @@ struct nvkm_bitfield {
const char *name;
};
void nvkm_bitfield_print(const struct nvkm_bitfield *, u32 value);
void nvkm_snprintbf(char *, int, const struct nvkm_bitfield *, u32 value);
#endif

16
drivers/gpu/drm/nouveau/nvkm/core/enum.c
View File

@ -49,22 +49,6 @@ nvkm_enum_print(const struct nvkm_enum *en, u32 value)
return en;
}
void
nvkm_bitfield_print(const struct nvkm_bitfield *bf, u32 value)
{
while (bf->name) {
if (value & bf->mask) {
pr_cont(" %s", bf->name);
value &= ~bf->mask;
}
bf++;
}
if (value)
pr_cont(" (unknown bits 0x%08x)", value);
}
void
nvkm_snprintbf(char *data, int size, const struct nvkm_bitfield *bf, u32 value)
{

5
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
View File

@ -1271,7 +1271,8 @@ int
gf100_grctx_generate(struct gf100_gr *gr)
{
struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass;
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bar *bar = device->bar;
struct nvkm_gpuobj *chan;
struct gf100_grctx info;
@ -1283,7 +1284,7 @@ gf100_grctx_generate(struct gf100_gr *gr)
ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size,
0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
if (ret) {
nv_error(gr, "failed to allocate channel memory, %d\n", ret);
nvkm_error(subdev, "failed to allocate chan memory, %d\n", ret);
return ret;
}

233
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -673,7 +673,8 @@ gf100_gr_zbc_init(struct gf100_gr *gr)
int
gf100_gr_wait_idle(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
bool gr_enabled, ctxsw_active, gr_busy;
@ -692,8 +693,9 @@ gf100_gr_wait_idle(struct gf100_gr *gr)
return 0;
} while (time_before(jiffies, end_jiffies));
nv_error(gr, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
gr_enabled, ctxsw_active, gr_busy);
nvkm_error(subdev,
"wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
gr_enabled, ctxsw_active, gr_busy);
return -EAGAIN;
}
@ -790,55 +792,50 @@ gf100_gr_units(struct nvkm_gr *obj)
return cfg;
}
static const struct nvkm_enum gk104_sked_error[] = {
{ 7, "CONSTANT_BUFFER_SIZE" },
{ 9, "LOCAL_MEMORY_SIZE_POS" },
{ 10, "LOCAL_MEMORY_SIZE_NEG" },
{ 11, "WARP_CSTACK_SIZE" },
{ 12, "TOTAL_TEMP_SIZE" },
{ 13, "REGISTER_COUNT" },
{ 18, "TOTAL_THREADS" },
{ 20, "PROGRAM_OFFSET" },
{ 21, "SHARED_MEMORY_SIZE" },
{ 25, "SHARED_CONFIG_TOO_SMALL" },
{ 26, "TOTAL_REGISTER_COUNT" },
static const struct nvkm_bitfield gk104_sked_error[] = {
{ 0x00000080, "CONSTANT_BUFFER_SIZE" },
{ 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
{ 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
{ 0x00000800, "WARP_CSTACK_SIZE" },
{ 0x00001000, "TOTAL_TEMP_SIZE" },
{ 0x00002000, "REGISTER_COUNT" },
{ 0x00040000, "TOTAL_THREADS" },
{ 0x00100000, "PROGRAM_OFFSET" },
{ 0x00200000, "SHARED_MEMORY_SIZE" },
{ 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
{ 0x04000000, "TOTAL_REGISTER_COUNT" },
{}
};
static const struct nvkm_enum gf100_gpc_rop_error[] = {
{ 1, "RT_PITCH_OVERRUN" },
{ 4, "RT_WIDTH_OVERRUN" },
{ 5, "RT_HEIGHT_OVERRUN" },
{ 7, "ZETA_STORAGE_TYPE_MISMATCH" },
{ 8, "RT_STORAGE_TYPE_MISMATCH" },
{ 10, "RT_LINEAR_MISMATCH" },
static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
{ 0x00000002, "RT_PITCH_OVERRUN" },
{ 0x00000010, "RT_WIDTH_OVERRUN" },
{ 0x00000020, "RT_HEIGHT_OVERRUN" },
{ 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
{ 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
{ 0x00000400, "RT_LINEAR_MISMATCH" },
{}
};
static void
gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
char error[128];
u32 trap[4];
int i;
trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420));
trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
nv_error(gr, "GPC%d/PROP trap:", gpc);
for (i = 0; i <= 29; ++i) {
if (!(trap[0] & (1 << i)))
continue;
pr_cont(" ");
nvkm_enum_print(gf100_gpc_rop_error, i);
}
pr_cont("\n");
nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n",
trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f,
trap[3] & 0xff);
nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
"format = %x, storage type = %x\n",
gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
(trap[2] >> 8) & 0x3f, trap[3] & 0xff);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
}
@ -864,17 +861,19 @@ static const struct nvkm_bitfield gf100_mp_global_error[] = {
static void
gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
const struct nvkm_enum *warp;
char glob[128];
nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc);
nvkm_bitfield_print(gf100_mp_global_error, gerr);
if (werr) {
pr_cont(" ");
nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff);
}
pr_cont("\n");
nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
"global %08x [%s] warp %04x [%s]\n",
gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
@ -883,12 +882,13 @@ gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
static void
gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
if (stat & 0x00000001) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
stat &= ~0x00000001;
}
@ -900,27 +900,28 @@ gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
if (stat & 0x00000004) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
stat &= ~0x00000008;
}
if (stat) {
nv_error(gr, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
}
}
static void
gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
int tpc;
@ -931,21 +932,21 @@ gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
if (stat & 0x00000002) {
u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
stat &= ~0x00000002;
}
if (stat & 0x00000004) {
u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
stat &= ~0x00000004;
}
if (stat & 0x00000008) {
u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
stat &= ~0x00000009;
}
@ -960,20 +961,21 @@ gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
}
if (stat) {
nv_error(gr, "GPC%d/0x%08x: unknown\n", gpc, stat);
nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
}
}
static void
gf100_gr_trap_intr(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 trap = nvkm_rd32(device, 0x400108);
int rop, gpc, i;
int rop, gpc;
if (trap & 0x00000001) {
u32 stat = nvkm_rd32(device, 0x404000);
nv_error(gr, "DISPATCH 0x%08x\n", stat);
nvkm_error(subdev, "DISPATCH %08x\n", stat);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000001);
trap &= ~0x00000001;
@ -981,7 +983,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
if (trap & 0x00000002) {
u32 stat = nvkm_rd32(device, 0x404600);
nv_error(gr, "M2MF 0x%08x\n", stat);
nvkm_error(subdev, "M2MF %08x\n", stat);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000002);
trap &= ~0x00000002;
@ -989,7 +991,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
if (trap & 0x00000008) {
u32 stat = nvkm_rd32(device, 0x408030);
nv_error(gr, "CCACHE 0x%08x\n", stat);
nvkm_error(subdev, "CCACHE %08x\n", stat);
nvkm_wr32(device, 0x408030, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000008);
trap &= ~0x00000008;
@ -997,7 +999,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
if (trap & 0x00000010) {
u32 stat = nvkm_rd32(device, 0x405840);
nv_error(gr, "SHADER 0x%08x\n", stat);
nvkm_error(subdev, "SHADER %08x\n", stat);
nvkm_wr32(device, 0x405840, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000010);
trap &= ~0x00000010;
@ -1005,7 +1007,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
if (trap & 0x00000040) {
u32 stat = nvkm_rd32(device, 0x40601c);
nv_error(gr, "UNK6 0x%08x\n", stat);
nvkm_error(subdev, "UNK6 %08x\n", stat);
nvkm_wr32(device, 0x40601c, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000040);
trap &= ~0x00000040;
@ -1013,25 +1015,20 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
if (trap & 0x00000080) {
u32 stat = nvkm_rd32(device, 0x404490);
nv_error(gr, "MACRO 0x%08x\n", stat);
nvkm_error(subdev, "MACRO %08x\n", stat);
nvkm_wr32(device, 0x404490, 0xc0000000);
nvkm_wr32(device, 0x400108, 0x00000080);
trap &= ~0x00000080;
}
if (trap & 0x00000100) {
u32 stat = nvkm_rd32(device, 0x407020);
u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
char sked[128];
nv_error(gr, "SKED:");
for (i = 0; i <= 29; ++i) {
if (!(stat & (1 << i)))
continue;
pr_cont(" ");
nvkm_enum_print(gk104_sked_error, i);
}
pr_cont("\n");
nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat);
nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked);
if (stat & 0x3fffffff)
if (stat)
nvkm_wr32(device, 0x407020, 0x40000000);
nvkm_wr32(device, 0x400108, 0x00000100);
trap &= ~0x00000100;
@ -1055,7 +1052,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
for (rop = 0; rop < gr->rop_nr; rop++) {
u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
nv_error(gr, "ROP%d 0x%08x 0x%08x\n",
nvkm_error(subdev, "ROP%d %08x %08x\n",
rop, statz, statc);
nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
@ -1065,7 +1062,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
}
if (trap) {
nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap);
nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
nvkm_wr32(device, 0x400108, trap);
}
}
@ -1073,15 +1070,20 @@ gf100_gr_trap_intr(struct gf100_gr *gr)
static void
gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nv_error(gr, "%06x - done 0x%08x\n", base,
nvkm_rd32(device, base + 0x400));
nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
nvkm_rd32(device, base + 0x800), nvkm_rd32(device, base + 0x804),
nvkm_rd32(device, base + 0x808), nvkm_rd32(device, base + 0x80c));
nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
nvkm_rd32(device, base + 0x810), nvkm_rd32(device, base + 0x814),
nvkm_rd32(device, base + 0x818), nvkm_rd32(device, base + 0x81c));
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
nvkm_error(subdev, "%06x - done %08x\n", base,
nvkm_rd32(device, base + 0x400));
nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
nvkm_rd32(device, base + 0x800),
nvkm_rd32(device, base + 0x804),
nvkm_rd32(device, base + 0x808),
nvkm_rd32(device, base + 0x80c));
nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
nvkm_rd32(device, base + 0x810),
nvkm_rd32(device, base + 0x814),
nvkm_rd32(device, base + 0x818),
nvkm_rd32(device, base + 0x81c));
}
void
@ -1099,7 +1101,8 @@ gf100_gr_ctxctl_debug(struct gf100_gr *gr)
static void
gf100_gr_ctxctl_isr(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x409c18);
if (stat & 0x00000001) {
@ -1111,26 +1114,26 @@ gf100_gr_ctxctl_isr(struct gf100_gr *gr)
u32 mthd = (addr & 0x00003ffc);
u32 data = nvkm_rd32(device, 0x409810);
nv_error(gr, "FECS MTHD subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
subc, class, mthd, data);
nvkm_error(subdev, "FECS MTHD subc %d class %04x "
"mthd %04x data %08x\n",
subc, class, mthd, data);
nvkm_wr32(device, 0x409c20, 0x00000001);
stat &= ~0x00000001;
} else {
nv_error(gr, "FECS ucode error %d\n", code);
nvkm_error(subdev, "FECS ucode error %d\n", code);
}
}
if (stat & 0x00080000) {
nv_error(gr, "FECS watchdog timeout\n");
nvkm_error(subdev, "FECS watchdog timeout\n");
gf100_gr_ctxctl_debug(gr);
nvkm_wr32(device, 0x409c20, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
nv_error(gr, "FECS 0x%08x\n", stat);
nvkm_error(subdev, "FECS %08x\n", stat);
gf100_gr_ctxctl_debug(gr);
nvkm_wr32(device, 0x409c20, stat);
}
@ -1175,10 +1178,10 @@ gf100_gr_intr(struct nvkm_subdev *subdev)
if (stat & 0x00000010) {
handle = nvkm_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) {
nv_error(gr,
"ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
"subc %d class %04x mthd %04x data %08x\n",
chid, inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
nvkm_handle_put(handle);
nvkm_wr32(device, 0x400100, 0x00000010);
@ -1186,27 +1189,29 @@ gf100_gr_intr(struct nvkm_subdev *subdev)
}
if (stat & 0x00000020) {
nv_error(gr,
"ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
"subc %d class %04x mthd %04x data %08x\n",
chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
nvkm_wr32(device, 0x400100, 0x00000020);
stat &= ~0x00000020;
}
if (stat & 0x00100000) {
nv_error(gr, "DATA_ERROR [");
nvkm_enum_print(nv50_data_error_names, code);
pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
const struct nvkm_enum *en =
nvkm_enum_find(nv50_data_error_names, code);
nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
"subc %d class %04x mthd %04x data %08x\n",
code, en ? en->name : "", chid, inst << 12,
nvkm_client_name(engctx), subc, class, mthd, data);
nvkm_wr32(device, 0x400100, 0x00100000);
stat &= ~0x00100000;
}
if (stat & 0x00200000) {
nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
nvkm_client_name(engctx));
nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
chid, inst << 12,
nvkm_client_name(engctx));
gf100_gr_trap_intr(gr);
nvkm_wr32(device, 0x400100, 0x00200000);
stat &= ~0x00200000;
@ -1219,7 +1224,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev)
}
if (stat) {
nv_error(gr, "unknown stat 0x%08x\n", stat);
nvkm_error(subdev, "intr %08x\n", stat);
nvkm_wr32(device, 0x400100, stat);
}
@ -1295,7 +1300,8 @@ gf100_gr_init_csdata(struct gf100_gr *gr,
int
gf100_gr_init_ctxctl(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass;
struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass;
int i;
@ -1390,7 +1396,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
if (gr->data == NULL) {
int ret = gf100_grctx_generate(gr);
if (ret) {
nv_error(gr, "failed to construct context\n");
nvkm_error(subdev, "failed to construct context\n");
return ret;
}
}
@ -1448,7 +1454,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
if (gr->data == NULL) {
int ret = gf100_grctx_generate(gr);
if (ret) {
nv_error(gr, "failed to construct context\n");
nvkm_error(subdev, "failed to construct context\n");
return ret;
}
}
@ -1580,7 +1586,8 @@ int
gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
struct gf100_gr_fuc *fuc)
{
struct nvkm_device *device = nv_device(gr);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
const struct firmware *fw;
char f[64];
char cname[16];
@ -1599,7 +1606,7 @@ gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname);
ret = request_firmware(&fw, f, nv_device_base(device));
if (ret) {
nv_error(gr, "failed to load %s\n", fwname);
nvkm_error(subdev, "failed to load %s\n", fwname);
return ret;
}
@ -1633,7 +1640,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_object **pobject)
{
struct gf100_gr_oclass *oclass = (void *)bclass;
struct nvkm_device *device = nv_device(parent);
struct nvkm_device *device = (void *)parent;
struct gf100_gr *gr;
bool use_ext_fw, enable;
int ret, i, j;
@ -1653,7 +1660,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
gr->base.units = gf100_gr_units;
if (use_ext_fw) {
nv_info(gr, "using external firmware\n");
nvkm_info(&gr->base.engine.subdev, "using external firmware\n");
if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||

7
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View File

@ -220,13 +220,14 @@ gk20a_gr_dtor(struct nvkm_object *object)
static int
gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
if (nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x40910c) & 0x00000006))
break;
) < 0) {
nv_error(gr, "FECS mem scrubbing timeout\n");
nvkm_error(subdev, "FECS mem scrubbing timeout\n");
return -ETIMEDOUT;
}
@ -234,7 +235,7 @@ gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr)
if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006))
break;
) < 0) {
nv_error(gr, "GPCCS mem scrubbing timeout\n");
nvkm_error(subdev, "GPCCS mem scrubbing timeout\n");
return -ETIMEDOUT;
}

27
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
View File

@ -1200,7 +1200,8 @@ bool
nv04_gr_idle(void *obj)
{
struct nvkm_gr *gr = nvkm_gr(obj);
struct nvkm_device *device = gr->engine.subdev.device;
struct nvkm_subdev *subdev = &gr->engine.subdev;
struct nvkm_device *device = subdev->device;
u32 mask = 0xffffffff;
if (nv_device(obj)->card_type == NV_40)
@ -1210,8 +1211,8 @@ nv04_gr_idle(void *obj)
if (!(nvkm_rd32(device, NV04_PGRAPH_STATUS) & mask))
break;
) < 0) {
nv_error(gr, "idle timed out with status 0x%08x\n",
nvkm_rd32(device, NV04_PGRAPH_STATUS));
nvkm_error(subdev, "idle timed out with status %08x\n",
nvkm_rd32(device, NV04_PGRAPH_STATUS));
return false;
}
@ -1276,6 +1277,7 @@ nv04_gr_intr(struct nvkm_subdev *subdev)
u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff;
u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4;
u32 show = stat;
char msg[128], src[128], sta[128];
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
@ -1303,17 +1305,14 @@ nv04_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv04_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv04_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(chan), subc, class, mthd,
data);
nvkm_snprintbf(msg, sizeof(msg), nv04_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv04_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
nvkm_client_name(chan), subc, class, mthd, data);
}
nvkm_namedb_put(handle);

29
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
View File

@ -690,6 +690,7 @@ static void
nv10_gr_create_pipe(struct nv10_gr_chan *chan)
{
struct nv10_gr *gr = nv10_gr(chan);
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct pipe_state *pipe_state = &chan->pipe_state;
u32 *pipe_state_addr;
int i;
@ -702,7 +703,7 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan)
u32 *__end_addr = pipe_state->pipe_##addr + \
ARRAY_SIZE(pipe_state->pipe_##addr); \
if (pipe_state_addr != __end_addr) \
nv_error(gr, "incomplete pipe init for 0x%x : %p/%p\n", \
nvkm_error(subdev, "incomplete pipe init for 0x%x : %p/%p\n", \
addr, pipe_state_addr, __end_addr); \
} while (0)
#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value
@ -844,24 +845,26 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan)
static int
nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
int i;
for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) {
if (nv10_gr_ctx_regs[i] == reg)
return i;
}
nv_error(gr, "unknow offset nv10_ctx_regs %d\n", reg);
nvkm_error(subdev, "unknow offset nv10_ctx_regs %d\n", reg);
return -1;
}
static int
nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
int i;
for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) {
if (nv17_gr_ctx_regs[i] == reg)
return i;
}
nv_error(gr, "unknow offset nv17_ctx_regs %d\n", reg);
nvkm_error(subdev, "unknow offset nv17_ctx_regs %d\n", reg);
return -1;
}
@ -1177,6 +1180,7 @@ nv10_gr_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
char msg[128], src[128], sta[128];
unsigned long flags;
spin_lock_irqsave(&gr->lock, flags);
@ -1204,17 +1208,14 @@ nv10_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(chan), subc, class, mthd,
data);
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
nvkm_client_name(chan), subc, class, mthd, data);
}
nvkm_namedb_put(handle);

20
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
View File

@ -207,6 +207,7 @@ nv20_gr_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
char msg[128], src[128], sta[128];
engctx = nvkm_engctx_get(engine, chid);
if (stat & NV_PGRAPH_INTR_ERROR) {
@ -222,17 +223,14 @@ nv20_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nvkm_client_name(engctx), subc, class, mthd,
data);
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
nvkm_client_name(engctx), subc, class, mthd, data);
}
nvkm_engctx_put(engctx);

26
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
View File

@ -155,7 +155,8 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv40_gr *gr = (void *)object->engine;
struct nv40_gr_chan *chan = (void *)object;
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
int ret = 0;
@ -172,7 +173,7 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
break;
) < 0) {
u32 insn = nvkm_rd32(device, 0x400308);
nv_warn(gr, "ctxprog timeout 0x%08x\n", insn);
nvkm_warn(subdev, "ctxprog timeout %08x\n", insn);
ret = -EBUSY;
}
}
@ -302,6 +303,7 @@ nv40_gr_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff;
u32 show = stat;
char msg[128], src[128], sta[128];
int chid;
engctx = nvkm_engctx_get(engine, inst);
@ -324,17 +326,15 @@ nv40_gr_intr(struct nvkm_subdev *subdev)
nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(gr,
"ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 4, nvkm_client_name(engctx), subc,
class, mthd, data);
nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
"nstatus %08x [%s] ch %d [%08x %s] subc %d "
"class %04x mthd %04x data %08x\n",
show, msg, nsource, src, nstatus, sta, chid,
inst << 4, nvkm_client_name(engctx), subc,
class, mthd, data);
}
nvkm_engctx_put(engctx);

277
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
View File

@ -200,46 +200,71 @@ static const struct nvkm_bitfield nv50_gr_status[] = {
{}
};
static const char *const nv50_gr_vstatus_0[] = {
"VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
NULL
static const struct nvkm_bitfield
nv50_gr_vstatus_0[] = {
{ 0x01, "VFETCH" },
{ 0x02, "CCACHE" },
{ 0x04, "PREGEOM" },
{ 0x08, "POSTGEOM" },
{ 0x10, "VATTR" },
{ 0x20, "STRMOUT" },
{ 0x40, "VCLIP" },
{}
};
static const char *const nv50_gr_vstatus_1[] = {
"TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
static const struct nvkm_bitfield
nv50_gr_vstatus_1[] = {
{ 0x01, "TPC_RAST" },
{ 0x02, "TPC_PROP" },
{ 0x04, "TPC_TEX" },
{ 0x08, "TPC_GEOM" },
{ 0x10, "TPC_MP" },
{}
};
static const char *const nv50_gr_vstatus_2[] = {
"RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
"ROP", NULL
static const struct nvkm_bitfield
nv50_gr_vstatus_2[] = {
{ 0x01, "RATTR" },
{ 0x02, "APLANE" },
{ 0x04, "TRAST" },
{ 0x08, "CLIPID" },
{ 0x10, "ZCULL" },
{ 0x20, "ENG2D" },
{ 0x40, "RMASK" },
{ 0x80, "ROP" },
{}
};
static void
nvkm_gr_vstatus_print(struct nv50_gr *gr, int r,
const char *const units[], u32 status)
const struct nvkm_bitfield *units, u32 status)
{
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
u32 stat = status;
u8 mask = 0x00;
char msg[64];
int i;
nv_error(gr, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
for (i = 0; units[i] && status; i++) {
for (i = 0; units[i].name && status; i++) {
if ((status & 7) == 1)
pr_cont(" %s", units[i]);
mask |= (1 << i);
status >>= 3;
}
if (status)
pr_cont(" (invalid: 0x%x)", status);
pr_cont("\n");
nvkm_snprintbf(msg, sizeof(msg), units, mask);
nvkm_error(subdev, "PGRAPH_VSTATUS%d: %08x [%s]\n", r, stat, msg);
}
static int
g84_gr_tlb_flush(struct nvkm_engine *engine)
{
struct nv50_gr *gr = (void *)engine;
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_timer *tmr = device->timer;
bool idle, timeout = false;
unsigned long flags;
char status[128];
u64 start;
u32 tmp;
@ -268,12 +293,11 @@ g84_gr_tlb_flush(struct nvkm_engine *engine)
!(timeout = tmr->read(tmr) - start > 2000000000));
if (timeout) {
nv_error(gr, "PGRAPH TLB flush idle timeout fail\n");
nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n");
tmp = nvkm_rd32(device, 0x400700);
nv_error(gr, "PGRAPH_STATUS : 0x%08x", tmp);
nvkm_bitfield_print(nv50_gr_status, tmp);
pr_cont("\n");
nvkm_snprintbf(status, sizeof(status), nv50_gr_status, tmp);
nvkm_error(subdev, "PGRAPH_STATUS %08x [%s]\n", tmp, status);
nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0,
nvkm_rd32(device, 0x400380));
@ -427,10 +451,10 @@ static const struct nvkm_bitfield nv50_gr_trap_prop[] = {
};
static void
nv50_gr_prop_trap(struct nv50_gr *gr,
u32 ustatus_addr, u32 ustatus, u32 tp)
nv50_gr_prop_trap(struct nv50_gr *gr, u32 ustatus_addr, u32 ustatus, u32 tp)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04);
u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08);
u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c);
@ -438,40 +462,44 @@ nv50_gr_prop_trap(struct nv50_gr *gr,
u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14);
u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18);
u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c);
char msg[128];
/* CUDA memory: l[], g[] or stack. */
if (ustatus & 0x00000080) {
if (e18 & 0x80000000) {
/* g[] read fault? */
nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
nvkm_error(subdev, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 24) & 0x1f));
e18 &= ~0x1f000000;
} else if (e18 & 0xc) {
/* g[] write fault? */
nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
nvkm_error(subdev, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
tp, e14, e10 | ((e18 >> 7) & 0x1f));
e18 &= ~0x00000f80;
} else {
nv_error(gr, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
nvkm_error(subdev, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
tp, e14, e10);
}
ustatus &= ~0x00000080;
}
if (ustatus) {
nv_error(gr, "TRAP_PROP - TP %d -", tp);
nvkm_bitfield_print(nv50_gr_trap_prop, ustatus);
pr_cont(" - Address %02x%08x\n", e14, e10);
nvkm_snprintbf(msg, sizeof(msg), nv50_gr_trap_prop, ustatus);
nvkm_error(subdev, "TRAP_PROP - TP %d - %08x [%s] - "
"Address %02x%08x\n",
tp, ustatus, msg, e14, e10);
}
nv_error(gr, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
nvkm_error(subdev, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
tp, e0c, e18, e1c, e20, e24);
}
static void
nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 units = nvkm_rd32(device, 0x1540);
u32 addr, mp10, status, pc, oplow, ophigh;
char msg[128];
int i;
int mps = 0;
for (i = 0; i < 4; i++) {
@ -490,19 +518,20 @@ nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display)
pc = nvkm_rd32(device, addr + 0x24);
oplow = nvkm_rd32(device, addr + 0x70);
ophigh = nvkm_rd32(device, addr + 0x74);
nv_error(gr, "TRAP_MP_EXEC - "
"TP %d MP %d:", tpid, i);
nvkm_bitfield_print(nv50_mp_exec_errors, status);
pr_cont(" at %06x warp %d, opcode %08x %08x\n",
pc&0xffffff, pc >> 24,
oplow, ophigh);
nvkm_snprintbf(msg, sizeof(msg),
nv50_mp_exec_errors, status);
nvkm_error(subdev, "TRAP_MP_EXEC - TP %d MP %d: "
"%08x [%s] at %06x warp %d, "
"opcode %08x %08x\n",
tpid, i, status, msg, pc & 0xffffff,
pc >> 24, oplow, ophigh);
}
nvkm_wr32(device, addr + 0x10, mp10);
nvkm_wr32(device, addr + 0x14, 0);
mps++;
}
if (!mps && display)
nv_error(gr, "TRAP_MP_EXEC - TP %d: "
nvkm_error(subdev, "TRAP_MP_EXEC - TP %d: "
"No MPs claiming errors?\n", tpid);
}
@ -510,10 +539,12 @@ static void
nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old,
u32 ustatus_new, int display, const char *name)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 units = nvkm_rd32(device, 0x1540);
int tps = 0;
int i, r;
char msg[128];
u32 ustatus_addr, ustatus;
for (i = 0; i < 16; i++) {
if (!(units & (1 << i)))
@ -529,15 +560,16 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old,
switch (type) {
case 6: /* texture error... unknown for now */
if (display) {
nv_error(gr, "magic set %d:\n", i);
nvkm_error(subdev, "magic set %d:\n", i);
for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
nv_error(gr, "\t0x%08x: 0x%08x\n", r,
nvkm_rd32(device, r));
nvkm_error(subdev, "\t%08x: %08x\n", r,
nvkm_rd32(device, r));
if (ustatus) {
nv_error(gr, "%s - TP%d:", name, i);
nvkm_bitfield_print(nv50_tex_traps,
ustatus);
pr_cont("\n");
nvkm_snprintbf(msg, sizeof(msg),
nv50_tex_traps, ustatus);
nvkm_error(subdev,
"%s - TP%d: %08x [%s]\n",
name, i, ustatus, msg);
ustatus = 0;
}
}
@ -548,9 +580,10 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old,
ustatus &= ~0x04030000;
}
if (ustatus && display) {
nv_error(gr, "%s - TP%d:", name, i);
nvkm_bitfield_print(nv50_mpc_traps, ustatus);
pr_cont("\n");
nvkm_snprintbf(msg, sizeof(msg),
nv50_mpc_traps, ustatus);
nvkm_error(subdev, "%s - TP%d: %08x [%s]\n",
name, i, ustatus, msg);
ustatus = 0;
}
break;
@ -563,25 +596,27 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old,
}
if (ustatus) {
if (display)
nv_error(gr, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
nvkm_error(subdev, "%s - TP%d: Unhandled ustatus %08x\n", name, i, ustatus);
}
nvkm_wr32(device, ustatus_addr, 0xc0000000);
}
if (!tps && display)
nv_warn(gr, "%s - No TPs claiming errors?\n", name);
nvkm_warn(subdev, "%s - No TPs claiming errors?\n", name);
}
static int
nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
int chid, u64 inst, struct nvkm_object *engctx)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 status = nvkm_rd32(device, 0x400108);
u32 ustatus;
char msg[128];
if (!status && display) {
nv_error(gr, "TRAP: no units reporting traps?\n");
nvkm_error(subdev, "TRAP: no units reporting traps?\n");
return 1;
}
@ -591,7 +626,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
if (status & 0x001) {
ustatus = nvkm_rd32(device, 0x400804) & 0x7fffffff;
if (!ustatus && display) {
nv_error(gr, "TRAP_DISPATCH - no ustatus?\n");
nvkm_error(subdev, "TRAP_DISPATCH - no ustatus?\n");
}
nvkm_wr32(device, 0x400500, 0x00000000);
@ -606,16 +641,19 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
u32 class = nvkm_rd32(device, 0x400814);
u32 r848 = nvkm_rd32(device, 0x400848);
nv_error(gr, "TRAP DISPATCH_FAULT\n");
nvkm_error(subdev, "TRAP DISPATCH_FAULT\n");
if (display && (addr & 0x80000000)) {
nv_error(gr,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
chid, inst,
nvkm_client_name(engctx), subc,
class, mthd, datah, datal, addr, r848);
nvkm_error(subdev,
"ch %d [%010llx %s] subc %d "
"class %04x mthd %04x data %08x%08x "
"400808 %08x 400848 %08x\n",
chid, inst,
nvkm_client_name(engctx),
subc, class, mthd,
datah, datal, addr, r848);
} else
if (display) {
nv_error(gr, "no stuck command?\n");
nvkm_error(subdev, "no stuck command?\n");
}
nvkm_wr32(device, 0x400808, 0);
@ -631,16 +669,17 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
u32 data = nvkm_rd32(device, 0x40085c);
u32 class = nvkm_rd32(device, 0x400814);
nv_error(gr, "TRAP DISPATCH_QUERY\n");
nvkm_error(subdev, "TRAP DISPATCH_QUERY\n");
if (display && (addr & 0x80000000)) {
nv_error(gr,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
chid, inst,
nvkm_client_name(engctx), subc,
class, mthd, data, addr);
nvkm_error(subdev,
"ch %d [%010llx %s] subc %d "
"class %04x mthd %04x data %08x "
"40084c %08x\n", chid, inst,
nvkm_client_name(engctx), subc,
class, mthd, data, addr);
} else
if (display) {
nv_error(gr, "no stuck command?\n");
nvkm_error(subdev, "no stuck command?\n");
}
nvkm_wr32(device, 0x40084c, 0);
@ -648,8 +687,8 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
}
if (ustatus && display) {
nv_error(gr, "TRAP_DISPATCH (unknown "
"0x%08x)\n", ustatus);
nvkm_error(subdev, "TRAP_DISPATCH "
"(unknown %08x)\n", ustatus);
}
nvkm_wr32(device, 0x400804, 0xc0000000);
@ -663,13 +702,15 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
if (status & 0x002) {
u32 ustatus = nvkm_rd32(device, 0x406800) & 0x7fffffff;
if (display) {
nv_error(gr, "TRAP_M2MF");
nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus);
pr_cont("\n");
nv_error(gr, "TRAP_M2MF %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x406804), nvkm_rd32(device, 0x406808),
nvkm_rd32(device, 0x40680c), nvkm_rd32(device, 0x406810));
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_m2mf, ustatus);
nvkm_error(subdev, "TRAP_M2MF %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_M2MF %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x406804),
nvkm_rd32(device, 0x406808),
nvkm_rd32(device, 0x40680c),
nvkm_rd32(device, 0x406810));
}
/* No sane way found yet -- just reset the bugger. */
@ -684,12 +725,15 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
if (status & 0x004) {
u32 ustatus = nvkm_rd32(device, 0x400c04) & 0x7fffffff;
if (display) {
nv_error(gr, "TRAP_VFETCH");
nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus);
pr_cont("\n");
nv_error(gr, "TRAP_VFETCH %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x400c00), nvkm_rd32(device, 0x400c08),
nvkm_rd32(device, 0x400c0c), nvkm_rd32(device, 0x400c10));
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_vfetch, ustatus);
nvkm_error(subdev, "TRAP_VFETCH %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_VFETCH %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x400c00),
nvkm_rd32(device, 0x400c08),
nvkm_rd32(device, 0x400c0c),
nvkm_rd32(device, 0x400c10));
}
nvkm_wr32(device, 0x400c04, 0xc0000000);
@ -701,13 +745,15 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
if (status & 0x008) {
ustatus = nvkm_rd32(device, 0x401800) & 0x7fffffff;
if (display) {
nv_error(gr, "TRAP_STRMOUT");
nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus);
pr_cont("\n");
nv_error(gr, "TRAP_STRMOUT %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x401804), nvkm_rd32(device, 0x401808),
nvkm_rd32(device, 0x40180c), nvkm_rd32(device, 0x401810));
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_strmout, ustatus);
nvkm_error(subdev, "TRAP_STRMOUT %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_STRMOUT %08x %08x %08x %08x\n",
nvkm_rd32(device, 0x401804),
nvkm_rd32(device, 0x401808),
nvkm_rd32(device, 0x40180c),
nvkm_rd32(device, 0x401810));
}
/* No sane way found yet -- just reset the bugger. */
@ -722,16 +768,19 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
if (status & 0x010) {
ustatus = nvkm_rd32(device, 0x405018) & 0x7fffffff;
if (display) {
nv_error(gr, "TRAP_CCACHE");
nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus);
pr_cont("\n");
nv_error(gr, "TRAP_CCACHE %08x %08x %08x %08x"
" %08x %08x %08x\n",
nvkm_rd32(device, 0x405000), nvkm_rd32(device, 0x405004),
nvkm_rd32(device, 0x405008), nvkm_rd32(device, 0x40500c),
nvkm_rd32(device, 0x405010), nvkm_rd32(device, 0x405014),
nvkm_rd32(device, 0x40501c));
nvkm_snprintbf(msg, sizeof(msg),
nv50_gr_trap_ccache, ustatus);
nvkm_error(subdev, "TRAP_CCACHE %08x [%s]\n",
ustatus, msg);
nvkm_error(subdev, "TRAP_CCACHE %08x %08x %08x %08x "
"%08x %08x %08x\n",
nvkm_rd32(device, 0x405000),
nvkm_rd32(device, 0x405004),
nvkm_rd32(device, 0x405008),
nvkm_rd32(device, 0x40500c),
nvkm_rd32(device, 0x405010),
nvkm_rd32(device, 0x405014),
nvkm_rd32(device, 0x40501c));
}
nvkm_wr32(device, 0x405018, 0xc0000000);
@ -745,7 +794,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
if (status & 0x20) {
ustatus = nvkm_rd32(device, 0x402000) & 0x7fffffff;
if (display)
nv_error(gr, "TRAP_UNKC04 0x%08x\n", ustatus);
nvkm_error(subdev, "TRAP_UNKC04 %08x\n", ustatus);
nvkm_wr32(device, 0x402000, 0xc0000000);
/* no status modifiction on purpose */
}
@ -777,7 +826,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display,
if (status) {
if (display)
nv_error(gr, "TRAP: unknown 0x%08x\n", status);
nvkm_error(subdev, "TRAP: unknown %08x\n", status);
nvkm_wr32(device, 0x400108, status);
}
@ -801,6 +850,8 @@ nv50_gr_intr(struct nvkm_subdev *subdev)
u32 data = nvkm_rd32(device, 0x400708);
u32 class = nvkm_rd32(device, 0x400814);
u32 show = stat, show_bitfield = stat;
const struct nvkm_enum *en;
char msg[128];
int chid;
engctx = nvkm_engctx_get(engine, inst);
@ -815,9 +866,9 @@ nv50_gr_intr(struct nvkm_subdev *subdev)
if (show & 0x00100000) {
u32 ecode = nvkm_rd32(device, 0x400110);
nv_error(gr, "DATA_ERROR ");
nvkm_enum_print(nv50_data_error_names, ecode);
pr_cont("\n");
en = nvkm_enum_find(nv50_data_error_names, ecode);
nvkm_error(subdev, "DATA_ERROR %08x [%s]\n",
ecode, en ? en->name : "");
show_bitfield &= ~0x00100000;
}
@ -833,15 +884,11 @@ nv50_gr_intr(struct nvkm_subdev *subdev)
if (show) {
show &= show_bitfield;
if (show) {
nv_error(gr, "%s", "");
nvkm_bitfield_print(nv50_gr_intr_name, show);
pr_cont("\n");
}
nv_error(gr,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
nvkm_snprintbf(msg, sizeof(msg), nv50_gr_intr_name, show);
nvkm_error(subdev, "%08x [%s] ch %d [%010llx %s] subc %d "
"class %04x mthd %04x data %08x\n",
stat, msg, chid, (u64)inst << 12,
nvkm_client_name(engctx), subc, class, mthd, data);
}
if (nvkm_rd32(device, 0x400824) & (1 << 31))