PCI: dwc: keystone: Use pci_ops for config space accessors
Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the TI Keystone driver to use the standard pci_ops for config accesses. Link: https://lore.kernel.org/r/20200821035420.380495-7-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
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@ -430,10 +430,10 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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ks_pcie_app_writel(ks_pcie, CMD_STATUS, val);
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}
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}
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static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where, int size,
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unsigned int devfn, int where)
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u32 *val)
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{
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{
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struct pcie_port *pp = bus->sysdata;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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u32 reg;
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u32 reg;
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@ -444,25 +444,14 @@ static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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reg |= CFG_TYPE1;
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reg |= CFG_TYPE1;
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ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
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ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
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return dw_pcie_read(pp->va_cfg0_base + where, size, val);
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return pp->va_cfg0_base + where;
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}
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}
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static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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static struct pci_ops ks_child_pcie_ops = {
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unsigned int devfn, int where, int size,
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.map_bus = ks_pcie_other_map_bus,
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u32 val)
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.read = pci_generic_config_read,
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{
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.write = pci_generic_config_write,
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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};
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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u32 reg;
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reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
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CFG_FUNC(PCI_FUNC(devfn));
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if (!pci_is_root_bus(bus->parent))
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reg |= CFG_TYPE1;
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ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
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return dw_pcie_write(pp->va_cfg0_base + where, size, val);
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}
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/**
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/**
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* ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
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* ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
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@ -490,6 +479,12 @@ static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp)
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
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}
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}
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static struct pci_ops ks_pcie_ops = {
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.map_bus = dw_pcie_own_conf_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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/**
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/**
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* ks_pcie_link_up() - Check if link up
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* ks_pcie_link_up() - Check if link up
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*/
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*/
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@ -807,6 +802,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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int ret;
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int ret;
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pp->bridge->ops = &ks_pcie_ops;
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pp->bridge->child_ops = &ks_child_pcie_ops;
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ret = ks_pcie_config_legacy_irq(ks_pcie);
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ret = ks_pcie_config_legacy_irq(ks_pcie);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@ -842,8 +840,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
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}
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}
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static const struct dw_pcie_host_ops ks_pcie_host_ops = {
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static const struct dw_pcie_host_ops ks_pcie_host_ops = {
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.rd_other_conf = ks_pcie_rd_other_conf,
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.wr_other_conf = ks_pcie_wr_other_conf,
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.host_init = ks_pcie_host_init,
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.host_init = ks_pcie_host_init,
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.msi_host_init = ks_pcie_msi_host_init,
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.msi_host_init = ks_pcie_msi_host_init,
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.scan_bus = ks_pcie_v3_65_scan_bus,
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.scan_bus = ks_pcie_v3_65_scan_bus,
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