From d400f209b4afe4a196baac276128eccac6a11b31 Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Thu, 16 May 2013 19:42:55 +0530 Subject: [PATCH 1/3] ARM: tegra: finalize USB EHCI and PHY bindings The existing Tegra USB bindings have a few issues: 1) Many properties are documented as being part of the EHCI controller node, yet they apply more to the PHY device. They should be moved. 2) Some registers in PHY1 are shared with PHY3, and hence PHY3 needs a reg entry to point at PHY1's register space. We can't assume the PHY1 driver is present, so the PHY3 driver will directly access those registers. 3) The list of clocks required by the PHY was missing some required entries. 4) UTMI PHY Timing parameters are added 5) VBUS control is now specified using a regulator rather than a plain GPIO 6) Added nvidia,is-wired property to indicate whether the device is hard wired on the board, or pluggable. This patch fixes the binding definition to resolve these issues. Signed-off-by: Venu Byravarasu Signed-off-by: Stephen Warren --- .../bindings/usb/nvidia,tegra20-ehci.txt | 27 +++--------- .../bindings/usb/nvidia,tegra20-usb-phy.txt | 41 +++++++++++++++++-- 2 files changed, 43 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt index 34c952883276..df0933043a5b 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt @@ -6,27 +6,10 @@ Practice : Universal Serial Bus" with the following modifications and additions : Required properties : - - compatible : Should be "nvidia,tegra20-ehci" for USB controllers - used in host mode. - - phy_type : Should be one of "ulpi" or "utmi". - - nvidia,vbus-gpio : If present, specifies a gpio that needs to be - activated for the bus to be powered. - - nvidia,phy : phandle of the PHY instance, the controller is connected to. - -Required properties for phy_type == ulpi: - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. + - compatible : Should be "nvidia,tegra20-ehci". + - nvidia,phy : phandle of the PHY that the controller is connected to. + - clocks : Contains a single entry which defines the USB controller's clock. Optional properties: - - dr_mode : dual role mode. Indicates the working mode for - nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", - or "otg". Default to "host" if not defined for backward compatibility. - host means this is a host controller - peripheral means it is device controller - otg means it can operate as either ("on the go") - - nvidia,has-legacy-mode : boolean indicates whether this controller can - operate in legacy mode (as APX 2500 / 2600). In legacy mode some - registers are accessed through the APB_MISC base address instead of - the USB controller. Since this is a legacy issue it probably does not - warrant a compatible string of its own. - - nvidia,needs-double-reset : boolean is to be set for some of the Tegra2 - USB ports, which need reset twice due to hardware issues. + - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 + USB ports, which need reset twice due to hardware issues. diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt index 6bdaba2f0aa1..c4c9e9e664aa 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt @@ -4,14 +4,49 @@ The device node for Tegra SOC USB PHY: Required properties : - compatible : Should be "nvidia,tegra20-usb-phy". - - reg : Address and length of the register set for the USB PHY interface. - - phy_type : Should be one of "ulpi" or "utmi". + - reg : Defines the following set of registers, in the order listed: + - The PHY's own register set. + Always present. + - The register set of the PHY containing the UTMI pad control registers. + Present if-and-only-if phy_type == utmi. + - phy_type : Should be one of "utmi", "ulpi" or "hsic". + - clocks : Defines the clocks listed in the clock-names property. + - clock-names : The following clock names must be present: + - reg: The clock needed to access the PHY's own registers. This is the + associated EHCI controller's clock. Always present. + - pll_u: PLL_U. Always present. + - timer: The timeout clock (clk_m). Present if phy_type == utmi. + - utmi-pads: The clock needed to access the UTMI pad control registers. + Present if phy_type == utmi. + - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2). + Present if phy_type == ulpi, and ULPI link mode is in use. Required properties for phy_type == ulpi: - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. +Required PHY timing params for utmi phy: + - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before + start of sync launches RxActive + - nvidia,elastic-limit : Variable FIFO Depth of elastic input store + - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait + before declare IDLE. + - nvidia,term-range-adj : Range adjusment on terminations + - nvidia,xcvr-setup : HS driver output control + - nvidia,xcvr-lsfslew : LS falling slew rate control. + - nvidia,xcvr-lsrslew : LS rising slew rate control. + Optional properties: - nvidia,has-legacy-mode : boolean indicates whether this controller can operate in legacy mode (as APX 2500 / 2600). In legacy mode some registers are accessed through the APB_MISC base address instead of - the USB controller. \ No newline at end of file + the USB controller. + - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power + optimizations for the devices that are always connected. e.g. modem. + - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be + "host", "peripheral", or "otg". Defaults to "host" if not defined. + host means this is a host controller + peripheral means it is device controller + otg means it can operate as either ("on the go") + +Required properties for dr_mode == otg: + - vbus-supply: regulator for VBUS From 9dffe3be3f321581c4510f2fa2e217b18c703bcd Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Thu, 16 May 2013 19:42:56 +0530 Subject: [PATCH 2/3] ARM: tegra: modify ULPI reset GPIO properties 1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active low nature of the GPIO. 2. Placed USB PHY DT node immediately below the EHCI controller DT nodes and corrected reg value in the name of USB PHY DT node. Signed-off-by: Venu Byravarasu Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 6 +++++- arch/arm/boot/dts/tegra20-harmony.dts | 10 +++++----- arch/arm/boot/dts/tegra20-paz00.dts | 10 +++++----- arch/arm/boot/dts/tegra20-seaboard.dts | 10 +++++----- arch/arm/boot/dts/tegra20-trimslice.dts | 10 +++++----- arch/arm/boot/dts/tegra20-ventana.dts | 10 +++++----- 6 files changed, 30 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index a573b94b7c93..c12af78e479c 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -449,7 +449,11 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ + }; + + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; sdhci@c8000600 { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index e7d5de4e00b9..e84f3f6a5392 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -430,17 +430,17 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ + }; + + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ - }; - sdhci@c8000200 { status = "okay"; cd-gpios = <&gpio 69 1>; /* gpio PI5 */ diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index e3e0c9977df4..e9ac2a991307 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -429,17 +429,17 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ + }; + + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ - }; - sdhci@c8000000 { status = "okay"; cd-gpios = <&gpio 173 1>; /* gpio PV5 */ diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index cee4c34010fe..9dd4f8ee4f4a 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -571,17 +571,17 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ + }; + + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ - }; - sdhci@c8000000 { status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 9cc78a15d739..fd7afd6b8306 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -316,17 +316,17 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ + nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ + }; + + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ - }; - sdhci@c8000000 { status = "okay"; bus-width = <4>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index dd38f1f03834..a75a0e78523f 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -507,17 +507,17 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ + }; + + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; usb@c5008000 { status = "okay"; }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ - }; - sdhci@c8000000 { status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ From 4c94c8b5b3cc38b0d0b1ec79642f5710e19a3e01 Mon Sep 17 00:00:00 2001 From: Venu Byravarasu Date: Thu, 16 May 2013 19:42:57 +0530 Subject: [PATCH 3/3] ARM: tegra: update device trees for USB binding rework This patch updates all Tegra board files so that they contain all the properties required by the updated USB DT binding. Note that this patch only adds the new properties and does not yet remove the old properties, in order to maintain bisectability. The old properties will be removed once the driver has been updated to assume the new bindings. Signed-off-by: Venu Byravarasu [swarren: fixed some newly added regulator-name properties to better match schematic, avoided duplicate regulator-name on Whistler.] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-harmony.dts | 9 +++++ arch/arm/boot/dts/tegra20-iris-512.dts | 9 ++++- arch/arm/boot/dts/tegra20-paz00.dts | 9 +++++ arch/arm/boot/dts/tegra20-seaboard.dts | 20 ++++++++++ arch/arm/boot/dts/tegra20-tamonten.dtsi | 4 ++ arch/arm/boot/dts/tegra20-trimslice.dts | 19 ++++++++++ arch/arm/boot/dts/tegra20-ventana.dts | 9 +++++ arch/arm/boot/dts/tegra20-whistler.dts | 28 ++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 49 +++++++++++++++++++------ 9 files changed, 143 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index e84f3f6a5392..ec5293758753 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -428,12 +428,17 @@ status = "okay"; }; + usb-phy@c5000000 { + status = "okay"; + }; + usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; usb-phy@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; @@ -441,6 +446,10 @@ status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000200 { status = "okay"; cd-gpios = <&gpio 69 1>; /* gpio PI5 */ diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index 52f1103907d7..9f64f7086881 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -38,13 +38,20 @@ usb@c5000000 { status = "okay"; - dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; }; usb@c5008000 { status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + serial@70006000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index e9ac2a991307..1c17ffaff1ad 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -427,12 +427,17 @@ status = "okay"; }; + usb-phy@c5000000 { + status = "okay"; + }; + usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ }; usb-phy@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ }; @@ -440,6 +445,10 @@ status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000000 { status = "okay"; cd-gpios = <&gpio 173 1>; /* gpio PV5 */ diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 9dd4f8ee4f4a..009dafecf88b 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -569,12 +569,19 @@ dr_mode = "otg"; }; + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; + dr_mode = "otg"; + }; + usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; usb-phy@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; @@ -582,6 +589,10 @@ status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000000 { status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ @@ -807,6 +818,15 @@ gpio = <&pmic 1 0>; enable-active-high; }; + + vbus_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_vbus_wup1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 24 0>; /* PD0 */ + }; }; sound { diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 50b3ec16b93a..fc2f7d6e70b2 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -470,6 +470,10 @@ status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000600 { cd-gpios = <&gpio 58 1>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index fd7afd6b8306..0e65c00ec732 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -314,12 +314,18 @@ nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */ }; + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; + }; + usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ }; usb-phy@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ }; @@ -327,6 +333,10 @@ status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000000 { status = "okay"; bus-width = <4>; @@ -390,6 +400,15 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + + vbus_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 170 0>; /* PV2 */ + }; }; sound { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index a75a0e78523f..e00f89e645f9 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -505,12 +505,17 @@ status = "okay"; }; + usb-phy@c5000000 { + status = "okay"; + }; + usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; usb-phy@c5004000 { + status = "okay"; nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; @@ -518,6 +523,10 @@ status = "okay"; }; + usb-phy@c5008000 { + status = "okay"; + }; + sdhci@c8000000 { status = "okay"; power-gpios = <&gpio 86 0>; /* gpio PK6 */ diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index d2567f83aaff..3c24c9b92b44 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -511,11 +511,21 @@ nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ }; + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus1_reg>; + }; + usb@c5008000 { status = "okay"; nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ }; + usb-phy@c5008000 { + status = "okay"; + vbus-supply = <&vbus3_reg>; + }; + sdhci@c8000400 { status = "okay"; cd-gpios = <&gpio 69 1>; /* gpio PI5 */ @@ -568,6 +578,24 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + vbus1_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vbus1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ + }; + + vbus3_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vbus3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ + }; }; sound { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 56a91106041b..96d6d8a3aa72 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -455,13 +455,24 @@ status = "disabled"; }; - phy1: usb-phy@c5000400 { + phy1: usb-phy@c5000000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5000400 0x3c00>; + reg = <0xc5000000 0x4000 0xc5000000 0x4000>; phy_type = "utmi"; + clocks = <&tegra_car 22>, + <&tegra_car 127>, + <&tegra_car 106>, + <&tegra_car 22>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; nvidia,has-legacy-mode; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; + hssync_start_delay = <9>; + idle_wait_delay = <17>; + elastic_limit = <16>; + term_range_adj = <6>; + xcvr_setup = <9>; + xcvr_lsfslew = <1>; + xcvr_lsrslew = <1>; + status = "disabled"; }; usb@c5004000 { @@ -474,12 +485,15 @@ status = "disabled"; }; - phy2: usb-phy@c5004400 { + phy2: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5004400 0x3c00>; + reg = <0xc5004000 0x4000>; phy_type = "ulpi"; - clocks = <&tegra_car 93>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; + clocks = <&tegra_car 58>, + <&tegra_car 127>, + <&tegra_car 93>; + clock-names = "reg", "pll_u", "ulpi-link"; + status = "disabled"; }; usb@c5008000 { @@ -492,12 +506,23 @@ status = "disabled"; }; - phy3: usb-phy@c5008400 { + phy3: usb-phy@c5008000 { compatible = "nvidia,tegra20-usb-phy"; - reg = <0xc5008400 0x3c00>; + reg = <0xc5008000 0x4000 0xc5000000 0x4000>; phy_type = "utmi"; - clocks = <&tegra_car 22>, <&tegra_car 127>; - clock-names = "phy", "pll_u"; + clocks = <&tegra_car 59>, + <&tegra_car 127>, + <&tegra_car 106>, + <&tegra_car 22>; + clock-names = "reg", "pll_u", "timer", "utmi-pads"; + hssync_start_delay = <9>; + idle_wait_delay = <17>; + elastic_limit = <16>; + term_range_adj = <6>; + xcvr_setup = <9>; + xcvr_lsfslew = <2>; + xcvr_lsrslew = <2>; + status = "disabled"; }; sdhci@c8000000 {