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clk: tegra: Unlock top rates for Tegra124 DFLL clock

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The new determine_rate prototype allows for clock rates exceeding
2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate
instead of round_rate and unlock the top rates supported by the
Tegra124.

Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Mikko Perttunen 2015-09-15 12:55:15 +03:00 committed by Thierry Reding
parent 6ff33f3902
commit 10d9be6ebe
2 changed files with 8 additions and 14 deletions
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15
drivers/clk/tegra/clk-dfll.c
View File

@ -1000,24 +1000,25 @@ static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,
return td->last_unrounded_rate; return td->last_unrounded_rate;
} }
static long dfll_clk_round_rate(struct clk_hw *hw, /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
unsigned long rate, static int dfll_clk_determine_rate(struct clk_hw *hw,
unsigned long *parent_rate) struct clk_rate_request *clk_req)
{ {
struct tegra_dfll *td = clk_hw_to_dfll(hw); struct tegra_dfll *td = clk_hw_to_dfll(hw);
struct dfll_rate_req req; struct dfll_rate_req req;
int ret; int ret;
ret = dfll_calculate_rate_request(td, &req, rate); ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
if (ret) if (ret)
return ret; return ret;
/* /*
* Don't return the rounded rate, since it doesn't really matter as * Don't set the rounded rate, since it doesn't really matter as
* the output rate will be voltage controlled anyway, and cpufreq * the output rate will be voltage controlled anyway, and cpufreq
* freaks out if any rounding happens. * freaks out if any rounding happens.
*/ */
return rate;
return 0;
} }
static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate, static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@ -1033,7 +1034,7 @@ static const struct clk_ops dfll_clk_ops = {
.enable = dfll_clk_enable, .enable = dfll_clk_enable,
.disable = dfll_clk_disable, .disable = dfll_clk_disable,
.recalc_rate = dfll_clk_recalc_rate, .recalc_rate = dfll_clk_recalc_rate,
.round_rate = dfll_clk_round_rate, .determine_rate = dfll_clk_determine_rate,
.set_rate = dfll_clk_set_rate, .set_rate = dfll_clk_set_rate,
}; };

7
drivers/clk/tegra/cvb.c
View File

@ -78,13 +78,6 @@ static int build_opp_table(const struct cvb_table *d,
if (!table->freq || (table->freq > max_freq)) if (!table->freq || (table->freq > max_freq))
break; break;
/*
* FIXME after clk_round_rate/clk_determine_rate prototypes
* have been updated
*/
if (table->freq & (1<<31))
continue;
dfll_mv = get_cvb_voltage( dfll_mv = get_cvb_voltage(
speedo_value, d->speedo_scale, &table->coefficients); speedo_value, d->speedo_scale, &table->coefficients);
dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale, align); dfll_mv = round_cvb_voltage(dfll_mv, d->voltage_scale, align);