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64-bit fixes for Alchemy code ;)

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2005-05-25 13:32:49 +00:00
parent ffd099bd33
commit 10f650db1b
1 changed files with 5 additions and 6 deletions
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11
arch/mips/kernel/cpu-probe.c
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@ -53,14 +53,13 @@ static void r4k_wait(void)
/* The Au1xxx wait is available only if using 32khz counter or /* The Au1xxx wait is available only if using 32khz counter or
* external timer source, but specifically not CP0 Counter. */ * external timer source, but specifically not CP0 Counter. */
int allow_au1k_wait; int allow_au1k_wait;
static void au1k_wait(void) static void au1k_wait(void)
{ {
unsigned long addr = 0;
/* using the wait instruction makes CP0 counter unusable */ /* using the wait instruction makes CP0 counter unusable */
__asm__("la %0,au1k_wait\n\t" __asm__(".set mips3\n\t"
".set mips3\n\t" "cache 0x14, 0(%0)\n\t"
"cache 0x14,0(%0)\n\t" "cache 0x14, 32(%0)\n\t"
"cache 0x14,32(%0)\n\t"
"sync\n\t" "sync\n\t"
"nop\n\t" "nop\n\t"
"wait\n\t" "wait\n\t"
@ -69,7 +68,7 @@ static void au1k_wait(void)
"nop\n\t" "nop\n\t"
"nop\n\t" "nop\n\t"
".set mips0\n\t" ".set mips0\n\t"
: : "r" (addr)); : : "r" (au1k_wait));
} }
static inline void check_wait(void) static inline void check_wait(void)