powerpc: dts: add missing space before {
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230705145743.292855-1-krzysztof.kozlowski@linaro.org
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@ -124,10 +124,10 @@
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reg = <0x80000 0x20000>;
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reg = <0x80000 0x20000>;
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ranges = <0x0 0x80000 0x20000>;
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ranges = <0x0 0x80000 0x20000>;
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jr@1000{
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jr@1000 {
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interrupts = <45 2 0 0>;
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interrupts = <45 2 0 0>;
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};
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};
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jr@2000{
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jr@2000 {
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interrupts = <57 2 0 0>;
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interrupts = <57 2 0 0>;
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};
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};
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};
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};
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@ -140,10 +140,10 @@
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reg = <0xa0000 0x20000>;
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reg = <0xa0000 0x20000>;
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ranges = <0x0 0xa0000 0x20000>;
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ranges = <0x0 0xa0000 0x20000>;
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jr@1000{
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jr@1000 {
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interrupts = <49 2 0 0>;
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interrupts = <49 2 0 0>;
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};
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};
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jr@2000{
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jr@2000 {
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interrupts = <50 2 0 0>;
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interrupts = <50 2 0 0>;
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};
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};
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};
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};
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@ -156,10 +156,10 @@
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reg = <0xc0000 0x20000>;
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reg = <0xc0000 0x20000>;
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ranges = <0x0 0xc0000 0x20000>;
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ranges = <0x0 0xc0000 0x20000>;
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jr@1000{
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jr@1000 {
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interrupts = <55 2 0 0>;
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interrupts = <55 2 0 0>;
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};
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};
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jr@2000{
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jr@2000 {
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interrupts = <56 2 0 0>;
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interrupts = <56 2 0 0>;
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};
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};
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};
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};
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@ -60,23 +60,23 @@
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compatible = "st,m41t62";
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compatible = "st,m41t62";
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reg = <0x68>;
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reg = <0x68>;
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};
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};
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adt7461@4c{
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adt7461@4c {
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compatible = "adi,adt7461";
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compatible = "adi,adt7461";
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reg = <0x4c>;
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reg = <0x4c>;
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};
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};
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zl6100@21{
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zl6100@21 {
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compatible = "isil,zl6100";
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compatible = "isil,zl6100";
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reg = <0x21>;
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reg = <0x21>;
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};
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};
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zl6100@24{
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zl6100@24 {
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compatible = "isil,zl6100";
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compatible = "isil,zl6100";
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reg = <0x24>;
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reg = <0x24>;
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};
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};
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zl6100@26{
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zl6100@26 {
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compatible = "isil,zl6100";
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compatible = "isil,zl6100";
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reg = <0x26>;
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reg = <0x26>;
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};
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};
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zl6100@29{
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zl6100@29 {
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compatible = "isil,zl6100";
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compatible = "isil,zl6100";
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reg = <0x29>;
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reg = <0x29>;
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};
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};
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@ -238,7 +238,7 @@
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fsl,has-rstcr;
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fsl,has-rstcr;
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};
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};
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power@e0070{
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power@e0070 {
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compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
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compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
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reg = <0xe0070 0x20>;
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reg = <0xe0070 0x20>;
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};
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};
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@ -41,7 +41,7 @@
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#size-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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interrupt-parent = <&mpic>;
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aliases{
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aliases {
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phy_rgmii_0 = &phy_rgmii_0;
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phy_rgmii_0 = &phy_rgmii_0;
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phy_rgmii_1 = &phy_rgmii_1;
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phy_rgmii_1 = &phy_rgmii_1;
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phy_sgmii_1c = &phy_sgmii_1c;
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phy_sgmii_1c = &phy_sgmii_1c;
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@ -165,7 +165,7 @@
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};
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};
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};
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};
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fman@400000{
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fman@400000 {
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ethernet@e0000 {
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ethernet@e0000 {
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phy-handle = <&phy_sgmii_1c>;
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phy-handle = <&phy_sgmii_1c>;
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phy-connection-type = "sgmii";
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phy-connection-type = "sgmii";
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@ -41,7 +41,7 @@
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#size-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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interrupt-parent = <&mpic>;
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aliases{
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aliases {
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phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
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phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
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phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
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phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
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phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
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phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
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@ -41,7 +41,7 @@
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#size-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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interrupt-parent = <&mpic>;
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aliases{
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aliases {
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phy_rgmii1 = &phyrgmii1;
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phy_rgmii1 = &phyrgmii1;
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phy_rgmii2 = &phyrgmii2;
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phy_rgmii2 = &phyrgmii2;
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phy_sgmii3 = &phy3;
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phy_sgmii3 = &phy3;
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@ -140,7 +140,7 @@
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};
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};
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/* Power Management Controller */
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/* Power Management Controller */
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pmc@1000{
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pmc@1000 {
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compatible = "fsl,mpc5121-pmc";
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compatible = "fsl,mpc5121-pmc";
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reg = <0x1000 0x100>;
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reg = <0x1000 0x100>;
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interrupts = <83 0x8>;
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interrupts = <83 0x8>;
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@ -104,7 +104,7 @@
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clock-names = "osc";
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clock-names = "osc";
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};
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};
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pmc@1000{ // Power Management Controller
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pmc@1000 { // Power Management Controller
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compatible = "fsl,mpc5121-pmc";
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compatible = "fsl,mpc5121-pmc";
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reg = <0x1000 0x100>;
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reg = <0x1000 0x100>;
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interrupts = <83 0x2>;
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interrupts = <83 0x2>;
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