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drm/msm: drop return from gpu->submit()

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At this point, there is nothing left to fail.  And submit already has a
fence assigned and is added to the submit_list.  Any problems from here
on out are asynchronous (ie. hangcheck/recovery).

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2016-05-03 09:46:49 -04:00
parent ed19075be1
commit 1193c3bcb5
4 changed files with 5 additions and 7 deletions
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4
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View File

@ -133,7 +133,7 @@ void adreno_recover(struct msm_gpu *gpu)
} }
} }
int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx) struct msm_file_private *ctx)
{ {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@ -212,8 +212,6 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
#endif #endif
gpu->funcs->flush(gpu); gpu->funcs->flush(gpu);
return 0;
} }
void adreno_flush(struct msm_gpu *gpu) void adreno_flush(struct msm_gpu *gpu)

2
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View File

@ -238,7 +238,7 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
int adreno_hw_init(struct msm_gpu *gpu); int adreno_hw_init(struct msm_gpu *gpu);
uint32_t adreno_last_fence(struct msm_gpu *gpu); uint32_t adreno_last_fence(struct msm_gpu *gpu);
void adreno_recover(struct msm_gpu *gpu); void adreno_recover(struct msm_gpu *gpu);
int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx); struct msm_file_private *ctx);
void adreno_flush(struct msm_gpu *gpu); void adreno_flush(struct msm_gpu *gpu);
void adreno_idle(struct msm_gpu *gpu); void adreno_idle(struct msm_gpu *gpu);

4
drivers/gpu/drm/msm/msm_gpu.c
View File

@ -540,12 +540,12 @@ int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
} }
ret = gpu->funcs->submit(gpu, submit, ctx); gpu->funcs->submit(gpu, submit, ctx);
priv->lastctx = ctx; priv->lastctx = ctx;
hangcheck_timer_reset(gpu); hangcheck_timer_reset(gpu);
return ret; return 0;
} }
/* /*

2
drivers/gpu/drm/msm/msm_gpu.h
View File

@ -47,7 +47,7 @@ struct msm_gpu_funcs {
int (*hw_init)(struct msm_gpu *gpu); int (*hw_init)(struct msm_gpu *gpu);
int (*pm_suspend)(struct msm_gpu *gpu); int (*pm_suspend)(struct msm_gpu *gpu);
int (*pm_resume)(struct msm_gpu *gpu); int (*pm_resume)(struct msm_gpu *gpu);
int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx); struct msm_file_private *ctx);
void (*flush)(struct msm_gpu *gpu); void (*flush)(struct msm_gpu *gpu);
void (*idle)(struct msm_gpu *gpu); void (*idle)(struct msm_gpu *gpu);