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arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name

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[ Upstream commit 52f4a10f2a860402c130c5c21d055e721d63a7e9 ]

DMA-related nodes have their own standardized naming. Therefore,
the MT8195 VDOSYS RDMA has been unified and corrected.
Additionally, these modifications will facilitate the further
integration of bindings.

Fixes: 92d2c23dc269 ("arm64: dts: mt8195: add display node for vdosys1")
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Moudy Ho 2023-10-30 17:48:39 +08:00 committed by Greg Kroah-Hartman
parent 4b0d8f4a68
commit 11f272928e
1 changed files with 16 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -2873,7 +2873,7 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
vdo1_rdma0: rdma@1c104000 {
vdo1_rdma0: dma-controller@1c104000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c104000 0 0x1000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2881,9 +2881,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
#dma-cells = <1>;
};
vdo1_rdma1: rdma@1c105000 {
vdo1_rdma1: dma-controller@1c105000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c105000 0 0x1000>;
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2891,9 +2892,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
#dma-cells = <1>;
};
vdo1_rdma2: rdma@1c106000 {
vdo1_rdma2: dma-controller@1c106000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c106000 0 0x1000>;
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2901,9 +2903,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
#dma-cells = <1>;
};
vdo1_rdma3: rdma@1c107000 {
vdo1_rdma3: dma-controller@1c107000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c107000 0 0x1000>;
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2911,9 +2914,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
#dma-cells = <1>;
};
vdo1_rdma4: rdma@1c108000 {
vdo1_rdma4: dma-controller@1c108000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c108000 0 0x1000>;
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2921,9 +2925,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
#dma-cells = <1>;
};
vdo1_rdma5: rdma@1c109000 {
vdo1_rdma5: dma-controller@1c109000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c109000 0 0x1000>;
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2931,9 +2936,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
#dma-cells = <1>;
};
vdo1_rdma6: rdma@1c10a000 {
vdo1_rdma6: dma-controller@1c10a000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c10a000 0 0x1000>;
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2941,9 +2947,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
#dma-cells = <1>;
};
vdo1_rdma7: rdma@1c10b000 {
vdo1_rdma7: dma-controller@1c10b000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c10b000 0 0x1000>;
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
@ -2951,6 +2958,7 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
#dma-cells = <1>;
};
merge1: vpp-merge@1c10c000 {