wifi: rtw89: 8852b: add chip_ops to read efuse
efuse stores individual data about a chip itself, such as MAC address, country code, RF and crystal calibration data, and so on. Define a struct to help access efuse content, and copy them into a common struct. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220928084336.34981-8-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
08484e1f6e
commit
132dc4fe5b
@ -24,6 +24,105 @@ static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
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NULL},
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};
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static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse,
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struct rtw8852b_efuse *map)
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{
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ether_addr_copy(efuse->addr, map->e.mac_addr);
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efuse->rfe_type = map->rfe_type;
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efuse->xtal_cap = map->xtal_k;
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}
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static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
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struct rtw8852b_efuse *map)
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{
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struct rtw89_tssi_info *tssi = &rtwdev->tssi;
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struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
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u8 i, j;
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tssi->thermal[RF_PATH_A] = map->path_a_therm;
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tssi->thermal[RF_PATH_B] = map->path_b_therm;
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for (i = 0; i < RF_PATH_NUM_8852B; i++) {
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memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
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sizeof(ofst[i]->cck_tssi));
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for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
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rtw89_debug(rtwdev, RTW89_DBG_TSSI,
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"[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
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i, j, tssi->tssi_cck[i][j]);
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memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
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sizeof(ofst[i]->bw40_tssi));
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memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
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ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
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for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
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rtw89_debug(rtwdev, RTW89_DBG_TSSI,
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"[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
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i, j, tssi->tssi_mcs[i][j]);
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}
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}
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static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
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{
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if (high)
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*high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);
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if (low)
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*low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);
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return data != 0xff;
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}
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static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
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struct rtw8852b_efuse *map)
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{
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struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
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bool valid = false;
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valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
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&gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
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&gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
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valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
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&gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
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&gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
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valid |= _decode_efuse_gain(map->rx_gain_5g_low,
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&gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
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&gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
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valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
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&gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
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&gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
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valid |= _decode_efuse_gain(map->rx_gain_5g_high,
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&gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
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&gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
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gain->offset_valid = valid;
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}
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static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
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{
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struct rtw89_efuse *efuse = &rtwdev->efuse;
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struct rtw8852b_efuse *map;
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map = (struct rtw8852b_efuse *)log_map;
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efuse->country_code[0] = map->country_code[0];
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efuse->country_code[1] = map->country_code[1];
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rtw8852b_efuse_parsing_tssi(rtwdev, map);
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rtw8852b_efuse_parsing_gain_offset(rtwdev, map);
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switch (rtwdev->hci.type) {
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case RTW89_HCI_TYPE_PCIE:
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rtw8852be_efuse_parsing(efuse, map);
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break;
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default:
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return -EOPNOTSUPP;
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}
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rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
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return 0;
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}
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static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
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enum rtw89_phy_idx phy_idx, s16 ref)
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{
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@ -269,6 +368,7 @@ static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
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static const struct rtw89_chip_ops rtw8852b_chip_ops = {
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.enable_bb_rf = rtw8852b_mac_enable_bb_rf,
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.disable_bb_rf = rtw8852b_mac_disable_bb_rf,
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.read_efuse = rtw8852b_read_efuse,
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.set_txpwr = rtw8852b_set_txpwr,
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.set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl,
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.init_txpwr_unit = rtw8852b_init_txpwr_unit,
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@ -280,6 +380,12 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
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.fifo_size = 196608,
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.dle_scc_rsvd_size = 98304,
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.dle_mem = rtw8852b_dle_mem_pcie,
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.sec_ctrl_efuse_size = 4,
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.physical_efuse_size = 1216,
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.logical_efuse_size = 2048,
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.limit_efuse_size = 1280,
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.dav_phy_efuse_size = 96,
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.dav_log_efuse_size = 16,
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.dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
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BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
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BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
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@ -10,4 +10,79 @@
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#define RF_PATH_NUM_8852B 2
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#define BB_PATH_NUM_8852B 2
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struct rtw8852b_u_efuse {
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u8 rsvd[0x88];
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u8 mac_addr[ETH_ALEN];
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};
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struct rtw8852b_e_efuse {
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u8 mac_addr[ETH_ALEN];
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};
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struct rtw8852b_tssi_offset {
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u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
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u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
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u8 rsvd[7];
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u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
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} __packed;
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struct rtw8852b_efuse {
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u8 rsvd[0x210];
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struct rtw8852b_tssi_offset path_a_tssi;
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u8 rsvd1[10];
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struct rtw8852b_tssi_offset path_b_tssi;
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u8 rsvd2[94];
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u8 channel_plan;
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u8 xtal_k;
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u8 rsvd3;
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u8 iqk_lck;
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u8 rsvd4[5];
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u8 reg_setting:2;
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u8 tx_diversity:1;
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u8 rx_diversity:2;
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u8 ac_mode:1;
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u8 module_type:2;
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u8 rsvd5;
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u8 shared_ant:1;
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u8 coex_type:3;
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u8 ant_iso:1;
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u8 radio_on_off:1;
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u8 rsvd6:2;
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u8 eeprom_version;
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u8 customer_id;
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u8 tx_bb_swing_2g;
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u8 tx_bb_swing_5g;
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u8 tx_cali_pwr_trk_mode;
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u8 trx_path_selection;
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u8 rfe_type;
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u8 country_code[2];
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u8 rsvd7[3];
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u8 path_a_therm;
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u8 path_b_therm;
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u8 rsvd8[2];
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u8 rx_gain_2g_ofdm;
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u8 rsvd9;
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u8 rx_gain_2g_cck;
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u8 rsvd10;
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u8 rx_gain_5g_low;
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u8 rsvd11;
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u8 rx_gain_5g_mid;
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u8 rsvd12;
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u8 rx_gain_5g_high;
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u8 rsvd13[35];
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u8 path_a_cck_pwr_idx[6];
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u8 path_a_bw40_1tx_pwr_idx[5];
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u8 path_a_ofdm_1tx_pwr_idx_diff:4;
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u8 path_a_bw20_1tx_pwr_idx_diff:4;
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u8 path_a_bw20_2tx_pwr_idx_diff:4;
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u8 path_a_bw40_2tx_pwr_idx_diff:4;
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u8 path_a_cck_2tx_pwr_idx_diff:4;
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u8 path_a_ofdm_2tx_pwr_idx_diff:4;
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u8 rsvd14[0xf2];
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union {
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struct rtw8852b_u_efuse u;
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struct rtw8852b_e_efuse e;
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};
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} __packed;
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#endif
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