dt-bindings: phy: Convert UniPhier USB3-PHY conroller to json-schema
Convert the UniPhier USB3-PHY controller for SS/HS to DT schema format. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Kunihiko Hayashi
Rob Herring
parent
60f4fc43ba
commit
134ab2845a
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier USB3 High-Speed (HS) PHY
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description: |
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This describes the devicetree bindings for PHY interfaces built into
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USB3 controller implemented on Socionext UniPhier SoCs.
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Although the controller includes High-Speed PHY and Super-Speed PHY,
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this describes about High-Speed PHY.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro5-usb3-hsphy
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- socionext,uniphier-pxs2-usb3-hsphy
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- socionext,uniphier-ld20-usb3-hsphy
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- socionext,uniphier-pxs3-usb3-hsphy
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reg:
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description: PHY register region (offset and length)
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"#phy-cells":
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const: 0
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- const: link # for PXs2
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- items: # for PXs3
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- const: link
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- const: phy
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: link
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- const: phy
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vbus-supply:
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description: A phandle to the regulator for USB VBUS
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nvmem-cells:
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maxItems: 3
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description:
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Phandles to nvmem cell that contains the trimming data.
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Available only for HS-PHY implemented on LD20 and PXs3, and
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if unspecified, default value is used.
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nvmem-cell-names:
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items:
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- const: rterm
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- const: sel_t
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- const: hs_i
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description:
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Should be the following names, which correspond to each nvmem-cells.
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All of the 3 parameters associated with the above names are
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required for each port, if any one is omitted, the trimming data
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of the port will not be set at all.
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_hsphy0: hs-phy@200 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus0>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
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};
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};
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@ -0,0 +1,96 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier USB3 Super-Speed (SS) PHY
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description: |
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This describes the devicetree bindings for PHY interfaces built into
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USB3 controller implemented on Socionext UniPhier SoCs.
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Although the controller includes High-Speed PHY and Super-Speed PHY,
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this describes about Super-Speed PHY.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro4-usb3-ssphy
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- socionext,uniphier-pro5-usb3-ssphy
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- socionext,uniphier-pxs2-usb3-ssphy
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- socionext,uniphier-ld20-usb3-ssphy
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- socionext,uniphier-pxs3-usb3-ssphy
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reg:
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description: PHY register region (offset and length)
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"#phy-cells":
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const: 0
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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oneOf:
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- items: # for Pro4, Pro5
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- const: gio
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- const: link
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- items: # for PXs3 with phy-ext
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- const: link
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- const: phy
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- const: phy-ext
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- items: # for others
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- const: link
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- const: phy
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resets:
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maxItems: 2
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reset-names:
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oneOf:
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- items: # for Pro4,Pro5
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- const: gio
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- const: link
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- items: # for others
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- const: link
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- const: phy
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vbus-supply:
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description: A phandle to the regulator for USB VBUS
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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- vbus-supply
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additionalProperties: false
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examples:
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- |
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_ssphy0: ss-phy@300 {
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compatible = "socionext,uniphier-ld20-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus0>;
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};
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};
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@ -1,69 +0,0 @@
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Socionext UniPhier USB3 High-Speed (HS) PHY
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This describes the devicetree bindings for PHY interfaces built into
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USB3 controller implemented on Socionext UniPhier SoCs.
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Although the controller includes High-Speed PHY and Super-Speed PHY,
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this describes about High-Speed PHY.
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Required properties:
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- compatible: Should contain one of the following:
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"socionext,uniphier-pro5-usb3-hsphy" - for Pro5 SoC
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"socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC
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"socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC
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"socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC
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- reg: Specifies offset and length of the register set for the device.
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- #phy-cells: Should be 0.
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- clocks: A list of phandles to the clock gate for USB3 glue layer.
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According to the clock-names, appropriate clocks are required.
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- clock-names: Should contain the following:
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"gio", "link" - for Pro5 SoC
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"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
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"phy", "link" - for others
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- resets: A list of phandles to the reset control for USB3 glue layer.
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According to the reset-names, appropriate resets are required.
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- reset-names: Should contain the following:
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"gio", "link" - for Pro5 SoC
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"phy", "link" - for others
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Optional properties:
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- vbus-supply: A phandle to the regulator for USB VBUS.
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- nvmem-cells: Phandles to nvmem cell that contains the trimming data.
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Available only for HS-PHY implemented on LD20 and PXs3, and
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if unspecified, default value is used.
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- nvmem-cell-names: Should be the following names, which correspond to
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each nvmem-cells.
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All of the 3 parameters associated with the following names are
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required for each port, if any one is omitted, the trimming data
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of the port will not be set at all.
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"rterm", "sel_t", "hs_i" - Each cell name for phy parameters
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Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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Example:
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_vbus0: regulator {
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...
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};
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usb_hsphy0: hs-phy@200 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus0>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
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<&usb_hs_i0>;
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};
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...
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};
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@ -1,58 +0,0 @@
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Socionext UniPhier USB3 Super-Speed (SS) PHY
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This describes the devicetree bindings for PHY interfaces built into
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USB3 controller implemented on Socionext UniPhier SoCs.
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Although the controller includes High-Speed PHY and Super-Speed PHY,
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this describes about Super-Speed PHY.
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Required properties:
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- compatible: Should contain one of the following:
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"socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
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"socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC
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"socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
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"socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
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"socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
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- reg: Specifies offset and length of the register set for the device.
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- #phy-cells: Should be 0.
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- clocks: A list of phandles to the clock gate for USB3 glue layer.
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According to the clock-names, appropriate clocks are required.
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- clock-names:
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"gio", "link" - for Pro4 and Pro5 SoC
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"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
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"phy", "link" - for others
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- resets: A list of phandles to the reset control for USB3 glue layer.
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According to the reset-names, appropriate resets are required.
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- reset-names:
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"gio", "link" - for Pro4 and Pro5 SoC
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"phy", "link" - for others
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Optional properties:
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- vbus-supply: A phandle to the regulator for USB VBUS.
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Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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Example:
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_vbus0: regulator {
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...
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};
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usb_ssphy0: ss-phy@300 {
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compatible = "socionext,uniphier-ld20-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus0>;
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};
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...
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};
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