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ARM: dts: renesas: r8a7740: Add LCDC nodes

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Add device nodes for the two LCD Controllers (LCDC) on the R-Mobile A1
SoC, and for the two optional external LCDL clock inputs.

Note that the HDMI clock for LCDC1 is not added, as this clock is not
yet supported.

Based on a patch by Laurent Pinchart adding the first LCDC device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/12dcec10e6fb3b55c39f6221349d35d6d6f17a5d.1700669207.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2023-11-22 17:12:42 +01:00
parent ea17f75131
commit 138588e9fa
1 changed files with 65 additions and 0 deletions
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65
arch/arm/boot/dts/renesas/r8a7740.dtsi
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@ -398,6 +398,61 @@
status = "disabled";
};
lcdc0: lcd-controller@fe940000 {
compatible = "renesas,r8a7740-lcdc";
reg = <0xfe940000 0x4000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
<&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
<&vou_clk>;
clock-names = "fck", "media", "lclk", "video";
power-domains = <&pd_a4lc>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lcdc0_rgb: endpoint {
};
};
};
};
lcdc1: lcd-controller@fe944000 {
compatible = "renesas,r8a7740-lcdc";
reg = <0xfe944000 0x4000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_LCDC1>,
<&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk1_clk>,
<&vou_clk>;
clock-names = "fck", "media", "lclk", "video";
power-domains = <&pd_a4lc>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lcdc1_rgb: endpoint {
};
};
port@1 {
reg = <1>;
lcdc1_hdmi: endpoint {
};
};
};
};
tmu0: timer@fff80000 {
compatible = "renesas,tmu-r8a7740", "renesas,tmu";
reg = <0xfff80000 0x2c>;
@ -474,6 +529,16 @@
#clock-cells = <0>;
clock-frequency = <0>;
};
lcdlclk0_clk: lcdlclk0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
lcdlclk1_clk: lcdlclk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {