x86/apic: Allow apic::safe_wait_icr_idle() to be NULL
Remove tons of NOOP callbacks by making the invocation of safe_wait_icr_idle() conditional in the inline wrapper. Will be replaced by a static_call_cond() later. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Juergen Gross <jgross@suse.com> # Xen PV (dom0 and unpriv. guest)
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@ -206,12 +206,6 @@ static inline u32 native_apic_msr_read(u32 reg)
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return (u32)msr;
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}
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static inline u32 native_safe_x2apic_wait_icr_idle(void)
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{
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/* no need to wait for icr idle in x2apic */
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return 0;
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}
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static inline void native_x2apic_icr_write(u32 low, u32 id)
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{
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wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
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@ -376,7 +370,7 @@ static inline void apic_wait_icr_idle(void)
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static inline u32 safe_apic_wait_icr_idle(void)
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{
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return apic->safe_wait_icr_idle();
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return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
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}
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extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
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@ -27,11 +27,6 @@ static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip)
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return -1;
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}
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static u32 noop_safe_apic_wait_icr_idle(void)
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{
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return 0;
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}
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static u64 noop_apic_icr_read(void)
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{
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return 0;
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@ -104,5 +99,4 @@ struct apic apic_noop __ro_after_init = {
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.eoi_write = noop_apic_write,
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.icr_read = noop_apic_icr_read,
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.icr_write = noop_apic_icr_write,
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.safe_wait_icr_idle = noop_safe_apic_wait_icr_idle,
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};
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@ -223,12 +223,6 @@ static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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return 1;
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}
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/* APIC NMI IPIs are queued */
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static u32 numachip_safe_apic_wait_icr_idle(void)
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{
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return 0;
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}
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static const struct apic apic_numachip1 __refconst = {
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.name = "NumaConnect system",
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.probe = numachip1_probe,
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@ -264,7 +258,6 @@ static const struct apic apic_numachip1 __refconst = {
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
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};
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apic_driver(apic_numachip1);
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@ -304,7 +297,6 @@ static const struct apic apic_numachip2 __refconst = {
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
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};
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apic_driver(apic_numachip2);
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@ -266,7 +266,6 @@ static struct apic apic_x2apic_cluster __ro_after_init = {
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.eoi_write = native_apic_msr_eoi_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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apic_driver(apic_x2apic_cluster);
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@ -180,7 +180,6 @@ static struct apic apic_x2apic_phys __ro_after_init = {
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.eoi_write = native_apic_msr_eoi_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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apic_driver(apic_x2apic_phys);
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@ -854,7 +854,6 @@ static struct apic apic_x2apic_uv_x __ro_after_init = {
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.eoi_write = native_apic_msr_eoi_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
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@ -92,11 +92,6 @@ static void xen_apic_icr_write(u32 low, u32 id)
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WARN_ON(1);
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}
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static u32 xen_safe_apic_wait_icr_idle(void)
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{
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return 0;
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}
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static int xen_apic_probe_pv(void)
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{
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if (xen_pv_domain())
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@ -161,7 +156,6 @@ static struct apic xen_pv_apic = {
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.icr_read = xen_apic_icr_read,
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.icr_write = xen_apic_icr_write,
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.safe_wait_icr_idle = xen_safe_apic_wait_icr_idle,
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};
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static void __init xen_apic_check(void)
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