x86/apic: Allow apic::safe_wait_icr_idle() to be NULL

Remove tons of NOOP callbacks by making the invocation of
safe_wait_icr_idle() conditional in the inline wrapper.

Will be replaced by a static_call_cond() later.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Sohil Mehta <sohil.mehta@intel.com>
Tested-by: Juergen Gross <jgross@suse.com> # Xen PV (dom0 and unpriv. guest)
This commit is contained in:
Thomas Gleixner 2023-08-08 15:04:05 -07:00 committed by Dave Hansen
parent ee513d9da3
commit 13d779fd26
7 changed files with 1 additions and 30 deletions

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@ -206,12 +206,6 @@ static inline u32 native_apic_msr_read(u32 reg)
return (u32)msr;
}
static inline u32 native_safe_x2apic_wait_icr_idle(void)
{
/* no need to wait for icr idle in x2apic */
return 0;
}
static inline void native_x2apic_icr_write(u32 low, u32 id)
{
wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
@ -376,7 +370,7 @@ static inline void apic_wait_icr_idle(void)
static inline u32 safe_apic_wait_icr_idle(void)
{
return apic->safe_wait_icr_idle();
return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
}
extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));

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@ -27,11 +27,6 @@ static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip)
return -1;
}
static u32 noop_safe_apic_wait_icr_idle(void)
{
return 0;
}
static u64 noop_apic_icr_read(void)
{
return 0;
@ -104,5 +99,4 @@ struct apic apic_noop __ro_after_init = {
.eoi_write = noop_apic_write,
.icr_read = noop_apic_icr_read,
.icr_write = noop_apic_icr_write,
.safe_wait_icr_idle = noop_safe_apic_wait_icr_idle,
};

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@ -223,12 +223,6 @@ static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
return 1;
}
/* APIC NMI IPIs are queued */
static u32 numachip_safe_apic_wait_icr_idle(void)
{
return 0;
}
static const struct apic apic_numachip1 __refconst = {
.name = "NumaConnect system",
.probe = numachip1_probe,
@ -264,7 +258,6 @@ static const struct apic apic_numachip1 __refconst = {
.eoi_write = native_apic_mem_write,
.icr_read = native_apic_icr_read,
.icr_write = native_apic_icr_write,
.safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
};
apic_driver(apic_numachip1);
@ -304,7 +297,6 @@ static const struct apic apic_numachip2 __refconst = {
.eoi_write = native_apic_mem_write,
.icr_read = native_apic_icr_read,
.icr_write = native_apic_icr_write,
.safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
};
apic_driver(apic_numachip2);

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@ -266,7 +266,6 @@ static struct apic apic_x2apic_cluster __ro_after_init = {
.eoi_write = native_apic_msr_eoi_write,
.icr_read = native_x2apic_icr_read,
.icr_write = native_x2apic_icr_write,
.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
};
apic_driver(apic_x2apic_cluster);

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@ -180,7 +180,6 @@ static struct apic apic_x2apic_phys __ro_after_init = {
.eoi_write = native_apic_msr_eoi_write,
.icr_read = native_x2apic_icr_read,
.icr_write = native_x2apic_icr_write,
.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
};
apic_driver(apic_x2apic_phys);

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@ -854,7 +854,6 @@ static struct apic apic_x2apic_uv_x __ro_after_init = {
.eoi_write = native_apic_msr_eoi_write,
.icr_read = native_x2apic_icr_read,
.icr_write = native_x2apic_icr_write,
.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
};
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3

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@ -92,11 +92,6 @@ static void xen_apic_icr_write(u32 low, u32 id)
WARN_ON(1);
}
static u32 xen_safe_apic_wait_icr_idle(void)
{
return 0;
}
static int xen_apic_probe_pv(void)
{
if (xen_pv_domain())
@ -161,7 +156,6 @@ static struct apic xen_pv_apic = {
.icr_read = xen_apic_icr_read,
.icr_write = xen_apic_icr_write,
.safe_wait_icr_idle = xen_safe_apic_wait_icr_idle,
};
static void __init xen_apic_check(void)