drm/nouveau/nvdec/r535: initial support
Adds support for allocating VIDEO_DECODER classes from RM. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-42-skeggsb@gmail.com
This commit is contained in:
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361c3cd8ae
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@ -198,6 +198,11 @@
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#define NV74_BSP 0x000074b0
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#define NVC4B0_VIDEO_DECODER 0x0000c4b0
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#define NVC6B0_VIDEO_DECODER 0x0000c6b0
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#define NVC7B0_VIDEO_DECODER 0x0000c7b0
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#define NVC9B0_VIDEO_DECODER 0x0000c9b0
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#define GT212_MSVLD 0x000085b1
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#define IGT21A_MSVLD 0x000086b1
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#define G98_MSVLD 0x000088b1
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@ -13,5 +13,7 @@ struct nvkm_nvdec {
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int gm107_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
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int tu102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
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int ga100_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
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int ga102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
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int ad102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
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#endif
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@ -57,6 +57,22 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
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typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO {
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NvU32 engDesc;
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NvU32 ctxAttr;
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NvU32 ctxBufferSize;
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NvU32 addrSpaceList;
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NvU32 registerBase;
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} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO;
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#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40
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#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
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typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
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NvU32 numConstructedFalcons;
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NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
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} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */
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typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS {
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@ -105,6 +105,13 @@ typedef struct
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NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel
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} NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS;
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typedef struct
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{
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NvU32 size;
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NvU32 prohibitMultipleInstances;
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NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2
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} NV_BSP_ALLOCATION_PARAMETERS;
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typedef struct
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{
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NvU32 index;
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@ -34,6 +34,12 @@
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#define MC_ENGINE_IDX_GSP 49
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#define MC_ENGINE_IDX_BSP 64
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#define MC_ENGINE_IDX_NVDEC MC_ENGINE_IDX_BSP
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#define MC_ENGINE_IDX_NVDEC0 MC_ENGINE_IDX_NVDEC
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#define MC_ENGINE_IDX_NVDEC7 71
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#define MC_ENGINE_IDX_GR 82
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#define MC_ENGINE_IDX_GR0 MC_ENGINE_IDX_GR
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@ -2592,6 +2592,7 @@ nv170_chipset = {
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.vfn = { 0x00000001, ga100_vfn_new },
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.ce = { 0x000003ff, ga100_ce_new },
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.fifo = { 0x00000001, ga100_fifo_new },
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.nvdec = { 0x0000001f, ga100_nvdec_new },
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};
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static const struct nvkm_device_chip
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@ -2763,6 +2764,7 @@ nv192_chipset = {
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.dma = { 0x00000001, gv100_dma_new },
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.fifo = { 0x00000001, ga102_fifo_new },
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.gr = { 0x00000001, ad102_gr_new },
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.nvdec = { 0x0000000f, ad102_nvdec_new },
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.sec2 = { 0x00000001, ga102_sec2_new },
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};
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@ -2785,6 +2787,7 @@ nv193_chipset = {
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.dma = { 0x00000001, gv100_dma_new },
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.fifo = { 0x00000001, ga102_fifo_new },
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.gr = { 0x00000001, ad102_gr_new },
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.nvdec = { 0x0000000f, ad102_nvdec_new },
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.sec2 = { 0x00000001, ga102_sec2_new },
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};
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@ -2807,6 +2810,7 @@ nv194_chipset = {
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.dma = { 0x00000001, gv100_dma_new },
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.fifo = { 0x00000001, ga102_fifo_new },
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.gr = { 0x00000001, ad102_gr_new },
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.nvdec = { 0x0000000f, ad102_nvdec_new },
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.sec2 = { 0x00000001, ga102_sec2_new },
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};
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@ -2829,6 +2833,7 @@ nv196_chipset = {
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.dma = { 0x00000001, gv100_dma_new },
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.fifo = { 0x00000001, ga102_fifo_new },
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.gr = { 0x00000001, ad102_gr_new },
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.nvdec = { 0x0000000f, ad102_nvdec_new },
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.sec2 = { 0x00000001, ga102_sec2_new },
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};
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@ -2851,6 +2856,7 @@ nv197_chipset = {
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.dma = { 0x00000001, gv100_dma_new },
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.fifo = { 0x00000001, ga102_fifo_new },
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.gr = { 0x00000001, ad102_gr_new },
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.nvdec = { 0x0000000f, ad102_nvdec_new },
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.sec2 = { 0x00000001, ga102_sec2_new },
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};
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@ -38,6 +38,8 @@
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/class/cl2080_notification.h>
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h>
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h>
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h>
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h>
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#include <nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h>
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#include <nvrm/535.54.03/nvidia/generated/g_kernel_channel_nvoc.h>
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#include <nvrm/535.54.03/nvidia/generated/g_kernel_fifo_nvoc.h>
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@ -378,6 +380,58 @@ r535_gr = {
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.ctor2 = r535_gr_ctor,
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};
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static int
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r535_flcn_bind(struct nvkm_engn *engn, struct nvkm_vctx *vctx, struct nvkm_chan *chan)
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{
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struct nvkm_gsp_client *client = &chan->vmm->rm.client;
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NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *ctrl;
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ctrl = nvkm_gsp_rm_ctrl_get(&chan->vmm->rm.device.subdevice,
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NV2080_CTRL_CMD_GPU_PROMOTE_CTX, sizeof(*ctrl));
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if (IS_ERR(ctrl))
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return PTR_ERR(ctrl);
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ctrl->hClient = client->object.handle;
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ctrl->hObject = chan->rm.object.handle;
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ctrl->hChanClient = client->object.handle;
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ctrl->virtAddress = vctx->vma->addr;
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ctrl->size = vctx->inst->size;
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ctrl->engineType = engn->id;
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ctrl->ChID = chan->id;
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return nvkm_gsp_rm_ctrl_wr(&chan->vmm->rm.device.subdevice, ctrl);
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}
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static int
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r535_flcn_ctor(struct nvkm_engn *engn, struct nvkm_vctx *vctx, struct nvkm_chan *chan)
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{
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int ret;
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if (WARN_ON(!engn->rm.size))
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return -EINVAL;
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ret = nvkm_gpuobj_new(engn->engine->subdev.device, engn->rm.size, 0, true, NULL,
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&vctx->inst);
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if (ret)
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return ret;
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ret = nvkm_vmm_get(vctx->vmm, 12, vctx->inst->size, &vctx->vma);
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if (ret)
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return ret;
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ret = nvkm_memory_map(vctx->inst, 0, vctx->vmm, vctx->vma, NULL, 0);
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if (ret)
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return ret;
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return r535_flcn_bind(engn, vctx, chan);
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}
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static const struct nvkm_engn_func
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r535_flcn = {
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.nonstall = r535_engn_nonstall,
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.ctor2 = r535_flcn_ctor,
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};
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static void
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r535_runl_allow(struct nvkm_runl *runl, u32 engm)
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{
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@ -447,6 +501,36 @@ r535_fifo_engn_type(RM_ENGINE_TYPE rm, enum nvkm_subdev_type *ptype)
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}
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}
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static int
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r535_fifo_ectx_size(struct nvkm_fifo *fifo)
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{
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NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *ctrl;
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struct nvkm_gsp *gsp = fifo->engine.subdev.device->gsp;
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struct nvkm_runl *runl;
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struct nvkm_engn *engn;
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ctrl = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice,
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NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO,
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sizeof(*ctrl));
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if (WARN_ON(IS_ERR(ctrl)))
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return PTR_ERR(ctrl);
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for (int i = 0; i < ctrl->numConstructedFalcons; i++) {
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nvkm_runl_foreach(runl, fifo) {
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nvkm_runl_foreach_engn(engn, runl) {
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if (engn->rm.desc == ctrl->constructedFalconsTable[i].engDesc) {
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engn->rm.size =
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ctrl->constructedFalconsTable[i].ctxBufferSize;
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break;
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}
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}
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}
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}
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nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
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return 0;
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}
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static int
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r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
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{
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@ -511,6 +595,9 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
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case NVKM_ENGINE_GR:
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engn = nvkm_runl_add(runl, nv2080, &r535_gr, type, inst);
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break;
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case NVKM_ENGINE_NVDEC:
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engn = nvkm_runl_add(runl, nv2080, &r535_flcn, type, inst);
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break;
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case NVKM_ENGINE_SW:
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continue;
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default:
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@ -522,6 +609,8 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
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nvkm_runl_del(runl);
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continue;
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}
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engn->rm.desc = ctrl->entries[i].engineData[ENGINE_INFO_TYPE_ENG_DESC];
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}
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nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
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@ -540,7 +629,7 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
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nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
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}
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return 0;
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return r535_fifo_ectx_size(fifo);
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}
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static void
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@ -29,6 +29,11 @@ struct nvkm_engn {
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int fault;
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struct {
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u32 desc;
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u32 size;
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} rm;
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struct list_head head;
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};
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@ -2,4 +2,8 @@
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nvkm-y += nvkm/engine/nvdec/base.o
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nvkm-y += nvkm/engine/nvdec/gm107.o
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nvkm-y += nvkm/engine/nvdec/tu102.o
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nvkm-y += nvkm/engine/nvdec/ga100.o
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nvkm-y += nvkm/engine/nvdec/ga102.o
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nvkm-y += nvkm/engine/nvdec/ad102.o
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nvkm-y += nvkm/engine/nvdec/r535.o
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44
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ad102.c
Normal file
44
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ad102.c
Normal file
@ -0,0 +1,44 @@
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/*
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* Copyright 2023 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/gsp.h>
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#include <nvif/class.h>
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static const struct nvkm_engine_func
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ad102_nvdec = {
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.sclass = {
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{ -1, -1, NVC9B0_VIDEO_DECODER },
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{}
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}
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};
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int
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ad102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_nvdec **pnvdec)
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{
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if (nvkm_gsp_rm(device->gsp))
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return r535_nvdec_new(&ad102_nvdec, device, type, inst, pnvdec);
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return -ENODEV;
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}
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44
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga100.c
Normal file
44
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga100.c
Normal file
@ -0,0 +1,44 @@
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/*
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* Copyright 2023 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/gsp.h>
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#include <nvif/class.h>
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static const struct nvkm_engine_func
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ga100_nvdec = {
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.sclass = {
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{ -1, -1, NVC6B0_VIDEO_DECODER },
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{}
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}
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};
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int
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ga100_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_nvdec **pnvdec)
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{
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if (nvkm_gsp_rm(device->gsp))
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return r535_nvdec_new(&ga100_nvdec, device, type, inst, pnvdec);
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return -ENODEV;
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}
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@ -22,8 +22,16 @@
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#include "priv.h"
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#include <subdev/gsp.h>
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#include <subdev/mc.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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static const struct nvkm_engine_func
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ga102_nvdec_gsp = {
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.sclass = {
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{ -1, -1, NVC7B0_VIDEO_DECODER },
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{}
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}
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};
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static const struct nvkm_falcon_func
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ga102_nvdec_flcn = {
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@ -59,7 +67,7 @@ ga102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst
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struct nvkm_nvdec **pnvdec)
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{
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if (nvkm_gsp_rm(device->gsp))
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return -ENODEV;
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return r535_nvdec_new(&ga102_nvdec_gsp, device, type, inst, pnvdec);
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return nvkm_nvdec_new_(ga102_nvdec_fwif, device, type, inst, 0x848000, pnvdec);
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}
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@ -5,6 +5,8 @@
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|
||||
struct nvkm_nvdec_func {
|
||||
const struct nvkm_falcon_func *flcn;
|
||||
|
||||
struct nvkm_sclass sclass[];
|
||||
};
|
||||
|
||||
struct nvkm_nvdec_fwif {
|
||||
@ -18,4 +20,7 @@ extern const struct nvkm_nvdec_fwif gm107_nvdec_fwif[];
|
||||
|
||||
int nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *,
|
||||
enum nvkm_subdev_type, int, u32 addr, struct nvkm_nvdec **);
|
||||
|
||||
int r535_nvdec_new(const struct nvkm_engine_func *, struct nvkm_device *,
|
||||
enum nvkm_subdev_type, int, struct nvkm_nvdec **);
|
||||
#endif
|
||||
|
110
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/r535.c
Normal file
110
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/r535.c
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright 2023 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "priv.h"
|
||||
|
||||
#include <core/object.h>
|
||||
#include <subdev/gsp.h>
|
||||
#include <engine/fifo.h>
|
||||
|
||||
#include <nvrm/nvtypes.h>
|
||||
#include <nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h>
|
||||
|
||||
struct r535_nvdec_obj {
|
||||
struct nvkm_object object;
|
||||
struct nvkm_gsp_object rm;
|
||||
};
|
||||
|
||||
static void *
|
||||
r535_nvdec_obj_dtor(struct nvkm_object *object)
|
||||
{
|
||||
struct r535_nvdec_obj *obj = container_of(object, typeof(*obj), object);
|
||||
|
||||
nvkm_gsp_rm_free(&obj->rm);
|
||||
return obj;
|
||||
}
|
||||
|
||||
static const struct nvkm_object_func
|
||||
r535_nvdec_obj = {
|
||||
.dtor = r535_nvdec_obj_dtor,
|
||||
};
|
||||
|
||||
static int
|
||||
r535_nvdec_obj_ctor(const struct nvkm_oclass *oclass, void *argv, u32 argc,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nvkm_chan *chan = nvkm_uchan_chan(oclass->parent);
|
||||
struct r535_nvdec_obj *obj;
|
||||
NV_BSP_ALLOCATION_PARAMETERS *args;
|
||||
|
||||
if (!(obj = kzalloc(sizeof(*obj), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
|
||||
nvkm_object_ctor(&r535_nvdec_obj, oclass, &obj->object);
|
||||
*pobject = &obj->object;
|
||||
|
||||
args = nvkm_gsp_rm_alloc_get(&chan->rm.object, oclass->handle, oclass->base.oclass,
|
||||
sizeof(*args), &obj->rm);
|
||||
if (WARN_ON(IS_ERR(args)))
|
||||
return PTR_ERR(args);
|
||||
|
||||
args->size = sizeof(*args);
|
||||
args->engineInstance = oclass->engine->subdev.inst;
|
||||
|
||||
return nvkm_gsp_rm_alloc_wr(&obj->rm, args);
|
||||
}
|
||||
|
||||
static void *
|
||||
r535_nvdec_dtor(struct nvkm_engine *engine)
|
||||
{
|
||||
struct nvkm_nvdec *nvdec = nvkm_nvdec(engine);
|
||||
|
||||
kfree(nvdec->engine.func);
|
||||
return nvdec;
|
||||
}
|
||||
|
||||
int
|
||||
r535_nvdec_new(const struct nvkm_engine_func *hw, struct nvkm_device *device,
|
||||
enum nvkm_subdev_type type, int inst, struct nvkm_nvdec **pnvdec)
|
||||
{
|
||||
struct nvkm_engine_func *rm;
|
||||
int nclass;
|
||||
|
||||
for (nclass = 0; hw->sclass[nclass].oclass; nclass++);
|
||||
|
||||
if (!(rm = kzalloc(sizeof(*rm) + (nclass + 1) * sizeof(rm->sclass[0]), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
|
||||
rm->dtor = r535_nvdec_dtor;
|
||||
for (int i = 0; i < nclass; i++) {
|
||||
rm->sclass[i].minver = hw->sclass[i].minver;
|
||||
rm->sclass[i].maxver = hw->sclass[i].maxver;
|
||||
rm->sclass[i].oclass = hw->sclass[i].oclass;
|
||||
rm->sclass[i].ctor = r535_nvdec_obj_ctor;
|
||||
}
|
||||
|
||||
if (!(*pnvdec = kzalloc(sizeof(**pnvdec), GFP_KERNEL))) {
|
||||
kfree(rm);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return nvkm_engine_ctor(rm, device, type, inst, true, &(*pnvdec)->engine);
|
||||
}
|
@ -23,12 +23,22 @@
|
||||
|
||||
#include <subdev/gsp.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
|
||||
static const struct nvkm_engine_func
|
||||
tu102_nvdec = {
|
||||
.sclass = {
|
||||
{ -1, -1, NVC4B0_VIDEO_DECODER },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
int
|
||||
tu102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
||||
struct nvkm_nvdec **pnvdec)
|
||||
{
|
||||
if (nvkm_gsp_rm(device->gsp))
|
||||
return -ENODEV;
|
||||
return r535_nvdec_new(&tu102_nvdec, device, type, inst, pnvdec);
|
||||
|
||||
return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, 0, pnvdec);
|
||||
}
|
||||
|
@ -859,6 +859,10 @@ r535_gsp_intr_get_table(struct nvkm_gsp *gsp)
|
||||
type = NVKM_ENGINE_GR;
|
||||
inst = 0;
|
||||
break;
|
||||
case MC_ENGINE_IDX_NVDEC0 ... MC_ENGINE_IDX_NVDEC7:
|
||||
type = NVKM_ENGINE_NVDEC;
|
||||
inst = ctrl->table[i].engineIdx - MC_ENGINE_IDX_NVDEC0;
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
Loading…
x
Reference in New Issue
Block a user