dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
Add bindings for the System-Top-Group clock and reset generator (STGCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu
Conor Dooley
parent
2110add84b
commit
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System-Top-Group Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-stgcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Main Oscillator (24 MHz)
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- description: HIFI4 core
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- description: STG AXI/AHB
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- description: USB (125 MHz)
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- description: CPU Bus
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- description: HIFI4 Axi
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- description: NOC STG Bus
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- description: APB Bus
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clock-names:
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items:
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- const: osc
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- const: hifi4_core
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- const: stg_axiahb
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- const: usb_125m
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- const: cpu_bus
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- const: hifi4_axi
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- const: nocstg_bus
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- const: apb_bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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stgcrg: clock-controller@10230000 {
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compatible = "starfive,jh7110-stgcrg";
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reg = <0x10230000 0x10000>;
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clocks = <&osc>,
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<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_USB_125M>,
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<&syscrg JH7110_SYSCLK_CPU_BUS>,
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<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
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<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
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<&syscrg JH7110_SYSCLK_APB_BUS>;
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clock-names = "osc", "hifi4_core",
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"stg_axiahb", "usb_125m",
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"cpu_bus", "hifi4_axi",
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"nocstg_bus", "apb_bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
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* Copyright 2022 StarFive Technology Co., Ltd.
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*/
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#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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@ -224,4 +225,37 @@
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#define JH7110_AONCLK_END 14
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/* STGCRG clocks */
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#define JH7110_STGCLK_HIFI4_CLK_CORE 0
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#define JH7110_STGCLK_USB0_APB 1
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#define JH7110_STGCLK_USB0_UTMI_APB 2
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#define JH7110_STGCLK_USB0_AXI 3
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#define JH7110_STGCLK_USB0_LPM 4
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#define JH7110_STGCLK_USB0_STB 5
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#define JH7110_STGCLK_USB0_APP_125 6
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#define JH7110_STGCLK_USB0_REFCLK 7
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#define JH7110_STGCLK_PCIE0_AXI_MST0 8
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#define JH7110_STGCLK_PCIE0_APB 9
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#define JH7110_STGCLK_PCIE0_TL 10
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#define JH7110_STGCLK_PCIE1_AXI_MST0 11
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#define JH7110_STGCLK_PCIE1_APB 12
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#define JH7110_STGCLK_PCIE1_TL 13
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#define JH7110_STGCLK_PCIE_SLV_MAIN 14
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#define JH7110_STGCLK_SEC_AHB 15
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#define JH7110_STGCLK_SEC_MISC_AHB 16
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#define JH7110_STGCLK_GRP0_MAIN 17
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#define JH7110_STGCLK_GRP0_BUS 18
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#define JH7110_STGCLK_GRP0_STG 19
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#define JH7110_STGCLK_GRP1_MAIN 20
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#define JH7110_STGCLK_GRP1_BUS 21
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#define JH7110_STGCLK_GRP1_STG 22
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#define JH7110_STGCLK_GRP1_HIFI 23
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#define JH7110_STGCLK_E2_RTC 24
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#define JH7110_STGCLK_E2_CORE 25
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#define JH7110_STGCLK_E2_DBG 26
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#define JH7110_STGCLK_DMA1P_AXI 27
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#define JH7110_STGCLK_DMA1P_AHB 28
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#define JH7110_STGCLK_END 29
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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@ -151,4 +152,31 @@
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#define JH7110_AONRST_END 8
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/* STGCRG resets */
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#define JH7110_STGRST_SYSCON 0
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#define JH7110_STGRST_HIFI4_CORE 1
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#define JH7110_STGRST_HIFI4_AXI 2
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#define JH7110_STGRST_SEC_AHB 3
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#define JH7110_STGRST_E24_CORE 4
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#define JH7110_STGRST_DMA1P_AXI 5
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#define JH7110_STGRST_DMA1P_AHB 6
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#define JH7110_STGRST_USB0_AXI 7
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#define JH7110_STGRST_USB0_APB 8
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#define JH7110_STGRST_USB0_UTMI_APB 9
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#define JH7110_STGRST_USB0_PWRUP 10
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#define JH7110_STGRST_PCIE0_AXI_MST0 11
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#define JH7110_STGRST_PCIE0_AXI_SLV0 12
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#define JH7110_STGRST_PCIE0_AXI_SLV 13
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#define JH7110_STGRST_PCIE0_BRG 14
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#define JH7110_STGRST_PCIE0_CORE 15
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#define JH7110_STGRST_PCIE0_APB 16
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#define JH7110_STGRST_PCIE1_AXI_MST0 17
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#define JH7110_STGRST_PCIE1_AXI_SLV0 18
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#define JH7110_STGRST_PCIE1_AXI_SLV 19
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#define JH7110_STGRST_PCIE1_BRG 20
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#define JH7110_STGRST_PCIE1_CORE 21
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#define JH7110_STGRST_PCIE1_APB 22
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#define JH7110_STGRST_END 23
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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