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arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux

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The SERDES lane control mux registers are present in the
CTRLMMR space.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-3-rogerq@ti.com
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Roger Quadros 2020-09-30 15:20:28 +03:00 committed by Nishanth Menon
parent ba90e0c926
commit 1509295295
1 changed files with 15 additions and 0 deletions
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15
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
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@ -18,6 +18,21 @@
};
};
scm_conf: scm-conf@100000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x00100000 0x00 0x1c000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
serdes_ln_ctrl: serdes-ln-ctrl@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;