clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clock
'ck_rtc' has multiple clocks as input (ck_hsi, ck_lsi, and ck_hse). A divider is available only on the specific rtc input for ck_hse. This Merge will facilitate to have a more coherent clock tree in no trusted / trusted world. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-3-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -245,7 +245,7 @@ static const char * const dsi_src[] = {
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};
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};
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static const char * const rtc_src[] = {
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static const char * const rtc_src[] = {
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"off", "ck_lse", "ck_lsi", "ck_hse_rtc"
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"off", "ck_lse", "ck_lsi", "ck_hse"
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};
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};
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static const char * const mco1_src[] = {
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static const char * const mco1_src[] = {
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@ -1031,6 +1031,47 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
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return hw;
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return hw;
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}
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}
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/* The divider of RTC clock concerns only ck_hse clock */
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#define HSE_RTC 3
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static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
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return clk_divider_ops.recalc_rate(hw, parent_rate);
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return parent_rate;
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}
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static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
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return clk_divider_ops.set_rate(hw, rate, parent_rate);
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return parent_rate;
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}
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static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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unsigned long best_parent_rate = req->best_parent_rate;
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if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) {
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req->rate = clk_divider_ops.round_rate(hw, req->rate, &best_parent_rate);
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req->best_parent_rate = best_parent_rate;
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} else {
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req->rate = best_parent_rate;
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}
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return 0;
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}
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static const struct clk_ops rtc_div_clk_ops = {
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.recalc_rate = clk_divider_rtc_recalc_rate,
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.set_rate = clk_divider_rtc_set_rate,
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.determine_rate = clk_divider_rtc_determine_rate
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};
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struct stm32_pll_cfg {
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struct stm32_pll_cfg {
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u32 offset;
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u32 offset;
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};
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};
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@ -1243,6 +1284,10 @@ _clk_stm32_register_composite(struct device *dev,
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_STM32_DIV(_div_offset, _div_shift, _div_width,\
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_STM32_DIV(_div_offset, _div_shift, _div_width,\
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_div_flags, _div_table, NULL)\
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_div_flags, _div_table, NULL)\
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#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
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_STM32_DIV(_div_offset, _div_shift, _div_width,\
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_div_flags, _div_table, &rtc_div_clk_ops)
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#define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
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#define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
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.mux = &(struct stm32_mux_cfg) {\
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.mux = &(struct stm32_mux_cfg) {\
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&(struct mux_cfg) {\
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&(struct mux_cfg) {\
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@ -1965,13 +2010,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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_DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
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_DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
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/* RTC clock */
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/* RTC clock */
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DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
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COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
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COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
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CLK_SET_RATE_PARENT,
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_GATE(RCC_BDCR, 20, 0),
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_GATE(RCC_BDCR, 20, 0),
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_MUX(RCC_BDCR, 16, 2, 0),
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_MUX(RCC_BDCR, 16, 2, 0),
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_NO_DIV),
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_DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
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/* MCO clocks */
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/* MCO clocks */
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COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
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COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
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