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soc: renesas: Make ARCH_R9A07G043 depend on required options

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Randy reported a randconfig build issue against linux-next:

    WARNING: unmet direct dependencies detected for ERRATA_ANDES
      Depends on [n]: RISCV_ALTERNATIVE [=n] && RISCV_SBI [=y]
      Selected by [y]:
      - ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] && NONPORTABLE [=y] && RISCV_SBI [=y]

    ../arch/riscv/errata/andes/errata.c:59:54: warning: 'struct alt_entry' declared inside parameter list will not be visible outside of this definition or declaration
       59 | void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,

On RISC-V, alternatives are not usable in XIP kernels, which this
randconfig happened to select.  Rather than add a check for whether
alternatives are available before selecting the ERRATA_ANDES config
option, rework the R9A07G043 Kconfig entry to depend on the
configuration options required to support its non-standard cache
coherency implementation.

Without these options enabled, the SoC is effectively non-functional to
begin with, so there's an extra benefit in preventing the creation of
non-functional kernels.

The "if RISCV_DMA_NONCOHERENT" can be dropped, as ERRATA_ANDES_CMO will
select it.

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Closes: https://lore.kernel.org/all/09a6b0f0-76a1-45e3-ab52-329c47393d1d@infradead.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231012-pouch-parkway-7d26c04b3300@spud
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Conor Dooley 2023-10-12 12:04:28 +01:00 committed by Geert Uytterhoeven
parent c1ec4b450a
commit 1531309aa2
1 changed files with 5 additions and 4 deletions
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9
drivers/soc/renesas/Kconfig
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@ -334,12 +334,13 @@ if RISCV
config ARCH_R9A07G043
bool "RISC-V Platform support for RZ/Five"
depends on NONPORTABLE
depends on RISCV_ALTERNATIVE
depends on RISCV_SBI
select ARCH_RZG2L
select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT
select AX45MP_L2_CACHE
select DMA_GLOBAL_POOL
select ERRATA_ANDES if RISCV_SBI
select ERRATA_ANDES_CMO if ERRATA_ANDES
select ERRATA_ANDES
select ERRATA_ANDES_CMO
help
This enables support for the Renesas RZ/Five SoC.